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PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE
117
Register 00CH, 10CH, 20CH, 30CH: SPLT Configuration
Bit
Type
Function
Default
Bit 7
R/W
FORM[1]
0
Bit 6
R/W
FORM[0]
0
Bit 5
R/W
M1TYPE
0
Bit 4
R/W
M2TYPE
0
Bit 3
R/W
FIXSTUFF
0
Bit 2
R/W
PLCPEN
0
Bit 1
Unused
X
Bit 0
R/W
EXT
0
EXT:
The EXT bit disables the internal transmission system sublayer timeslot
counter from identifying DS1, DS3, E1, J2, E3 G.751, or E3 G.832 overhead
bits. The EXT bit allows transmission formats that are unsupported by the
internal timeslot counter and must be supported using the TIOHM[x] input.
When a logic 0 is written to EXT, input transmission system overhead (for
DS1, DS3, E1, J2, E3 G.751, and E3 G.832 formats) is indicated using the
internal timeslot counter. This counter flywheels to create the appropriate
transmission system alignment. This alignment is indicated on the TOHM[x]
output. When a logic 1 is written to EXT, indications on TIOHM[x] identify
each transmission system overhead bit. These indications flow through the
S/UNI-QJET and appear on the TOHM[x] output where they mark the
transmission system overhead placeholder positions in the TDATO[x] stream.
EXT should only be set to logic 1 if the TFRM[1:0] bits in the S/UNI-QJET
Transmit Configuration register are both set to logic 1 and the arbitrary
framing format is desired.
PLCPEN:
The PLCPEN bit enables PLCP frame insertion. When a logic 1 is written to
PLCPEN, DS3, E3 G.751, DS1, or E1 PLCP framing is inserted. The PLCP
format is specified by the FORM[1:0] bits in this register. When a logic 0 is
written to PLCPEN, PLCP related functions in the SPLT block are disabled.
The PLCPEN bit must be set to logic 0 for G.832 E3, J2, and arbitrary
framing formats.