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PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE
179
pulse of the same polarity to the previous bipolar violation. To generate
another LCV, the DLCV register bit must be first be written to logic 0 and then
to logic 1 again.
DFERR:
The DFERR bit selects whether the framing pattern is corrupted for
diagnostic purposes. When DFERR is logic 1, the framing pattern inserted
into the output data stream is inverted. When DFERR is logic 0, the unaltered
framing pattern inserted into the output data stream.
CPERR:
The CPERR bit enables continuous generation of BIP-8 errors for diagnostic
purposes. When CPERR is logic 1, the calculated BIP-8 value is continuously
inverted according to the error mask specified by the BIP-8 Error Mask
register and inserted into the G.832 EM byte. When CPERR is logic 0, the
calculated BIP-8 value is altered only once, according to the error mask
specified by the BIP-8 Error Mask register, and inserted into the EM byte.
PYLD&JUST:
The PYLD&JUST bit selects whether the justification service bits and the
tributary justification bits in framing modes G.751 is indicated as overhead or
payload. When PYLD&JUST is logic 1, the justification service bits and the
tributary justification bits are indicated as payload. When PYLD&JUST is
logic 0, the justification service and tributary justification bits are indicated as
overhead. For G.751 ATM applications, this bit must be set to logic 1 for
correct cell mapping.