![](http://datasheet.mmic.net.cn/330000/PM7346_datasheet_16444391/PM7346_126.png)
PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE
105
Register 006H: S/UNI-QJET Identification, Master Reset, and Global
Monitor Update
Bit
Type
Function
Default
Bit 7
R/W
RESET
0
Bit 6
R
TYPE[3]
1
Bit 5
R
TYPE[2]
0
Bit 4
R
TYPE[1]
0
Bit 3
R
TYPE[0]
0
Bit 2
R
TIP
X
Bit 1
R
ID[1]
1
Bit 0
R
ID[0]
0
This register is used for global performance monitor updates, global software
resets, and for device identification. Writing any value except 80H into this
register initiates latching of all performance monitor counts in the PMON, RXCP-
50, and TXCP-50 blocks in all four quadrants of the S/UNI-QJET. The TIP register
bit is used to signal when the latching is complete.
The CPPM counter registers are
not
latched by writing to register 006H.
Counters in the CPPM can only be updated by writing to CPPM register
addresses (x22H – x2FH).
RESET:
The RESET bit allows software to asynchronously reset the S/UNI-QJET. The
software reset is equivalent to setting the RSTB input pin low, except that the
S/UNI-QJET Master Test Register is not affected. When a logic 1 is written to
RESET, the S/UNI-QJET is reset. When a logic 0 is written to RESET, the
reset is removed. The RESET bit must be explicitly set and cleared by writing
the corresponding logic value to this register.
TYPE[3:0]:
The TYPE[3:0] bits allow software to identify this device as the S/UNI-QJET
member of the S/UNI family of products.
TIP:
The TIP bit is set to a logic one when any value is written to this register.
Such a write initiates an accumulation interval transfer and loads all the