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PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE
109
Register 008H, 108H, 208H, 308H: SPLR Configuration
Bit
Type
Function
Default
Bit 7
R/W
FORM[1]
0
Bit 6
R/W
FORM[0]
0
Bit 5
R/W
Reserved
0
Bit 4
R/W
Reserved
0
Bit 3
R/W
REFRAME
0
Bit 2
R/W
PLCPEN
0
Bit 1
Unused
X
Bit 0
R/W
EXT
0
EXT:
The EXT bit disables the internal transmission system sublayer timeslot
counter from identifying DS1, DS3, E1, J2, E3 G.751, or E3 G.832 overhead
bits. The EXT bit allows transmission formats that are unsupported by the
internal timeslot counter to be supported using the ROHM[x] input. When a
logic 0 is written to EXT, input transmission system overhead (for DS1, DS3,
E1, J2, E3 G.751, and E3 G.832 formats) is indicated using the internal
timeslot counter. This counter is synchronized to the transmission system
frame alignment using the ROHM[x] (for DS1 or E1 ATM direct-mapped
formats), or by the integral framer block (for the DS3, J2, E3 G.751, or E3
G.832 formats).
When a logic 1 is written to EXT, indications on ROHM[x] identify each
transmission system overhead bit.
PLCPEN:
The PLCPEN bit enables PLCP framing. When a logic 1 is written to
PLCPEN, PLCP framing is enabled. The PLCP format is specified by the
FORM[1:0] bits in this register. When a logic 0 is written to PLCPEN, PLCP
related functions in the SPLR block are disabled. PLCPEN must be
programmed to logic 0 for E3 G.832, J2, and arbitrary framing formats.
REFRAME:
The REFRAME bit is used to trigger reframing. When a logic 1 is written to
REFRAME, the S/UNI-QJET is forced out of PLCP frame and a new search