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參數(shù)資料
型號： PIC18LF96J65-I/PT
廠商： Microchip Technology
文件頁數(shù)： 69/131頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 48KX16 100TQFP
標(biāo)準(zhǔn)包裝： 90
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 41.667MHz
連通性： EBI/EMI，以太網(wǎng)，I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 70
程序存儲器容量： 96KB（48K x 16）
程序存儲器類型： 閃存
RAM 容量： 3808 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TQFP
包裝： 托盤
PIC18F97J60 FAMILY
DS39762F-page 42
2011 Microchip Technology Inc.
NC
9
—
No connect.
VSS
15, 36, 40,
60, 65, 85
P
—
Ground reference for logic and I/O pins.
VDD
17, 37, 59,
62, 86
P
—
Positive supply for peripheral digital logic and I/O pins.
AVSS
31
P
—
Ground reference for analog modules.
AVDD
30
P
—
Positive supply for analog modules.
ENVREG
29
I
ST
Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
VCAP
16
P
—
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator enabled).
VSSPLL
82
P
—
Ground reference for Ethernet PHY PLL.
VDDPLL
81
P
—
Positive 3.3V supply for Ethernet PHY PLL.
VSSTX
79
P
—
Ground reference for Ethernet PHY transmit subsystem.
VDDTX
76
P
—
Positive 3.3V supply for Ethernet PHY transmit subsystem.
VSSRX
72
P
—
Ground reference for Ethernet PHY receive subsystem.
VDDRX
75
P
—
Positive 3.3V supply for Ethernet PHY receive subsystem.
RBIAS
80
I
Analog Bias current for Ethernet PHY. Must be tied to VSS via a resistor;
TPOUT+
78
O
—
Ethernet differential signal output.
TPOUT-
77
O
—
Ethernet differential signal output.
TPIN+
74
I
Analog Ethernet differential signal input.
TPIN-
73
I
Analog Ethernet differential signal input.
TABLE 1-6:
PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend:
TTL = TTL compatible input
CMOS
= CMOS compatible input or output
ST
= Schmitt Trigger input with CMOS levels
Analog
= Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1:
Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
2:
Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
3:
Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4:
Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
5:
Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
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