參數(shù)資料
型號： PIC18LF96J65-I/PT
廠商： Microchip Technology
文件頁數(shù)： 11/131頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 48KX16 100TQFP
標(biāo)準(zhǔn)包裝： 90
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 41.667MHz
連通性： EBI/EMI，以太網(wǎng)，I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 70
程序存儲器容量： 96KB（48K x 16）
程序存儲器類型： 閃存
RAM 容量： 3808 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TQFP
包裝： 托盤
PIC18F97J60 FAMILY
DS39762F-page 108
2011 Microchip Technology Inc.
7.2.2
TABLE LATCH REGISTER (TABLAT)
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
7.2.3
TABLE POINTER REGISTER
(TBLPTR)
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the Device ID and Configuration bits.
The Table Pointer register, TBLPTR, is used by the
TBLRD
and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 7-1. The table operations on the TBLPTR only
affect the low-order 21 bits.
7.2.4
TABLE POINTER BOUNDARIES
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
When a TBLWT is executed, the six LSbs of the Table
Pointer register (TBLPTR<5:0>) determine which of
the 64 program memory holding registers is written to.
When the timed write to program memory begins (via
the WR bit), the 15 MSbs of the TBLPTR
(TBLPTR<20:6>) determine which program memory
block of 64 bytes is written to. For more detail, see
.
When an erase of program memory is executed, the
11 MSbs of the Table Pointer register (TBLPTR<20:10>)
point to the 1024-byte block that will be erased. The
Least Significant bits (TBLPTR<9:0>) are ignored.
Figure 7-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE 7-1:
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
FIGURE 7-3:
TABLE POINTER BOUNDARIES BASED ON OPERATION
Example
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLRD*-
TBLWT*-
TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+*
TBLPTR is incremented before the read/write
21
16
15
87
0
Table Write
Table Read – TBLPTR<21:0>
TBLPTRL
TBLPTRH
TBLPTRU
TBLPTR<20:6>
Table Erase
TBLPTR<20:10>
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