參數(shù)資料
型號： PIC18LF96J65-I/PT
廠商： Microchip Technology
文件頁數(shù)： 20/131頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 48KX16 100TQFP
標準包裝： 90
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 41.667MHz
連通性： EBI/EMI，以太網(wǎng)，I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 70
程序存儲器容量： 96KB（48K x 16）
程序存儲器類型： 閃存
RAM 容量： 3808 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TQFP
包裝： 托盤
PIC18F97J60 FAMILY
DS39762F-page 116
2011 Microchip Technology Inc.
8.1
External Memory Bus Control
The operation of the interface is controlled by the
MEMCON register (Register 8-1). This register is
available in all program memory operating modes,
except Microcontroller mode. In this mode, the register
is disabled and cannot be written to.
The EBDIS bit (MEMCON<7>) controls the operation
of the bus and related port functions. Clearing EBDIS
enables the interface and disables the I/O functions of
the ports, as well as any other functions multiplexed to
those pins. Setting the bit enables the I/O ports and
other functions, but allows the interface to override
everything else on the pins when an external memory
operation is required. By default, the external bus is
always enabled and disables all other I/Os.
The operation of the EBDIS bit is also influenced by the
program memory mode being used. This is discussed
.
The WAIT bits allow for the addition of Wait states to
external memory operations. The use of these bits is
The WM bits select the particular operating mode used
when the bus is operating in 16-Bit Data Width mode.
These operating modes are discussed in more detail in
. The WM bits
have no effect when an 8-Bit Data Width mode is
selected.
REGISTER 8-1:
MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
R/W-0
EBDIS
—WAIT1
WAIT0
—
—WM1
WM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EBDIS
: External Bus Disable bit
1
= External bus is enabled when microcontroller accesses external memory; otherwise, all external
bus drivers are mapped as I/O ports
0
= External bus is always enabled, I/O ports are disabled
bit 6
Unimplemented:
Read as ‘0’
bit 5-4
WAIT<1:0>:
Table Reads and Writes Bus Cycle Wait Count bits
11
= Table reads and writes will wait 0 TCY
10
= Table reads and writes will wait 1 TCY
01
= Table reads and writes will wait 2 TCY
00
= Table reads and writes will wait 3 TCY
bit 3-2
Unimplemented:
Read as ‘0’
bit 1-0
WM<1:0>: TBLWT
Operation with 16-Bit Data Bus Width Select bits
1x
= Word Write mode: WRH is active when TABLAT is written to and TBLPTR contains an odd
address. When TBLPTR contains an even address, writing to TABLAT loads a holding latch with
the value written.
01
= Byte Select mode: TABLAT data is copied on both MSB and LSB; WRH and (UB or LB)
will activate
00
= Byte Write mode: TABLAT data is copied on both MSB and LSB; WRH or WRL will activate
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