參數資料
型號: PIC16F818
廠商: Microchip Technology Inc.
英文描述: 18/20-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology(18/20引腳,納瓦技術增強FLASH微控制器)
中文描述: 18/20-Pin增強型閃存微控制器采用納瓦技術(18/20引腳,納瓦技術增強閃存微控制器)
文件頁數: 86/164頁
文件大?。?/td> 3045K
代理商: PIC16F818
PIC16F818/819
DS39598C-page 84
Preliminary
2002 Microchip Technology Inc.
11.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
HOLD
) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-2. The source
impedance (R
S
) and the internal sampling switch (R
SS
)
impedance directly affect the time required to charge
the capacitor C
HOLD
. The sampling switch (R
SS
)
impedance varies over the device voltage (V
DD
), see
Figure 11-2.
The maximum recommended imped-
ance for analog sources is 2.5 k
.
As the impedance
is decreased, the acquisition time may be decreased.
After the analog input channel is selected (changed),
this acquisition must be done before the conversion
can be started.
To
Equation 11-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
calculate
the
minimum
acquisition
time,
To calculate the minimum acquisition time, T
ACQ
, see
the
PICmicro
Mid-Range
(DS33023).
Reference
Manual
EQUATION 11-1:
ACQUISITION TIME
FIGURE 11-2:
ANALOG INPUT MODEL
T
ACQ
T
C
T
ACQ
=
=
=
=
=
=
=
=
Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
T
AMP
+ T
C
+ T
COFF
2
μ
s + T
C
+ [(Temperature -25
°
C)(0.05
μ
s/°C)]
C
HOLD
(R
IC
+ R
SS
+ R
S
) In(1/2047)
-120 pF (1 k
+ 7 k
+ 10 k
) In(0.0004885)
16.47
μ
s
2
μ
s + 16.47
μ
s + [(50°C – 25
°
C)(0.05
μ
s/
°
C)
19.72
μ
s
Note 1:
The reference voltage (V
REF
) has no effect on the equation, since it cancels itself out.
2:
The charge holding capacitor (C
HOLD
) is not discharged after each conversion.
3:
The maximum recommended impedance for analog sources is 10 k
. This is required to meet the pin
leakage specification.
4:
After a conversion has completed, a 2.0 T
AD
delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
C
PIN
5 pF
VA
Rs
ANx
V
DD
V
T
= 0.6V
V
T
= 0.6V
I leakage
±
500 nA
R
IC
1k
Sampling
Switch
SS
R
SS
C
HOLD
= DAC capacitance
= 51.2 pF
V
SS
6 V
5 V
4 V
3 V
2 V
Sampling Switch
(k
)
5 6 7 8 9 10 11
V
DD
Legend: C
PIN
V
T
I leakage
R
IC
SS
C
HOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
various junctions
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
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