參數(shù)資料
型號(hào): PIC16F818
廠商: Microchip Technology Inc.
英文描述: 18/20-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology(18/20引腳,納瓦技術(shù)增強(qiáng)FLASH微控制器)
中文描述: 18/20-Pin增強(qiáng)型閃存微控制器采用納瓦技術(shù)(18/20引腳,納瓦技術(shù)增強(qiáng)閃存微控制器)
文件頁(yè)數(shù): 41/164頁(yè)
文件大?。?/td> 3045K
代理商: PIC16F818
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2002 Microchip Technology Inc.
Preliminary
DS39598C-page 39
PIC16F818/819
5.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
PICmicro Mid-Range Reference Manual (DS33023).
5.1
PORTA and the TRISA Register
PORTA is a 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register, reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified, and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input and with analog input to become the RA4/AN4/
T0CKI pin. The RA4/AN4/T0CKI pin is a Schmitt
Trigger input and full CMOS output driver.
Pin RA5 is multiplexed with the Master Clear module
input. The RA5/MCLR/V
PP
pin is a Schmitt Trigger
input.
Pin RA6 is multiplexed with the Oscillator module input
and External Oscillator output. Pin RA7 is multiplexed
with the Oscillator module input and External Oscillator
input. Pin RA6/OSC2/CLKO and pin RA7/OSC1/CLKI
are Schmitt Trigger inputs and full CMOS output drivers.
Pins RA<1:0> are multiplexed with analog inputs. Pins
RA<3:2> are multiplexed with analog inputs and V
REF
inputs. Pins RA<3:0> have TTL inputs and full CMOS
output drivers.
EXAMPLE 5-1:
INITIALIZING PORTA
TABLE 5-1:
PORTA FUNCTIONS
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Note:
On
PORTA<4:0> are configured as analog
inputs and read as '0'.
a
Power-on
Reset,
the
pins
BANKSEL PORTA
CLRF
; select bank of PORTA
; Initialize PORTA by
; clearing output
; data latches
; Select Bank of ADCON1
; Configure all pins
; as digital inputs
; Value used to
; initialize data
; direction
; Set RA<7:0> as inputs
PORTA
BANKSEL ADCON1
MOVLW
MOVWF
MOVLW
0x06
ADCON1
0xFF
MOVWF
TRISA
Name
Bit#
Buffer
Function
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/V
REF
RA4/AN4/T0CKI
RA5/MCLR/V
PP
RA6/OSC2/CLKO
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
TTL
TTL
TTL
TTL
ST
ST
ST
Input/output or analog input.
Input/output or analog input.
Input/output or analog input or V
REF-
.
Input/output or analog input or V
REF+.
Input/output, analog input or external clock input for Timer0.
Input, Master Clear (Reset) or Programming voltage input.
Input/output, connects to Crystal or Resonator, Oscillator output, or 1/4 the
frequency of OSC1, and denotes the instruction cycle in RC mode.
Input/output, connects to Crystal or Resonator or Oscillator input.
RA7/OSC1/CLKI
bit 7
ST/CMOS
(1)
Legend:
Note 1:
TTL = TTL input, ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other RESETS
05h
PORTA
(1)
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxx0 0000
uuu0 0000
85h
TRISA
TRISA7 TRISA6 TRISA5 PORTA Data Direction Register
1111 1111
1111 1111
9Fh
ADCON1
ADFM
ADCS2
PCFG3 PCFG2
PCFG1
PCFG0
00-- 0000
00-- 0000
Legend:
x
= unknown,
u
= unchanged,
-
= unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1:
PORTA pin 5 is an input only, the state of the TRISA5 bit has no effect and will always read ‘1’.
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