參數(shù)資料
型號： PIC16F818
廠商： Microchip Technology Inc.
英文描述： 18/20-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology(18/20引腳，納瓦技術(shù)增強(qiáng)FLASH微控制器)
中文描述： 18/20-Pin增強(qiáng)型閃存微控制器采用納瓦技術(shù)（18/20引腳，納瓦技術(shù)增強(qiáng)閃存微控制器）
文件頁數(shù)： 101/164頁
文件大?。?/td> 3045K
代理商： PIC16F818
2002 Microchip Technology Inc.
Preliminary
DS39598C-page 99
PIC16F818/819
12.13 Power-down Mode (SLEEP)
Power-down mode is entered by executing a
SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the
SLEEP
instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either V
DD
or V
SS
, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at V
DD
or V
SS
for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should also be considered.
The MCLR pin must be at a logic high level (V
IHMC
).
12.13.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
2.
External RESET input on MCLR pin.
Watchdog Timer wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change or a
peripheral interrupt.
3.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of the device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred and caused
wake-up.
The following peripheral interrupts can wake the device
from SLEEP:
1.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
CCP Capture mode interrupt.
Special event trigger (Timer1 in Asynchronous
mode using an external clock).
SSP (START/STOP) bit detect interrupt.
SSP transmit or receive in Slave mode (SPI/I
2
C).
A/D conversion (when A/D clock source is RC).
EEPROM write operation completion.
2.
3.
4.
5.
6.
7.
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
When the
SLEEP
instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the instruction after the
SLEEP
instruction. If the GIE bit
is set (enabled), the device executes the instruction
after the
SLEEP
instruction and then branches to the
interrupt address (0004h). In cases where the execu-
tion of the instruction following
SLEEP
is not desirable,
the user should have a
NOP
after the
SLEEP
instruction.
12.13.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
If the interrupt occurs
before
the execution of a
SLEEP
instruction, the
SLEEP
instruction will com-
plete as a
NOP
. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bit will not be cleared.
If the interrupt occurs
during or after
the
execution of a
SLEEP
instruction, the device will
immediately wake-up from SLEEP. The
SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP
instruction, it may be possible for flag bits to
become set before the
SLEEP
instruction completes. To
determine whether a
SLEEP
instruction executed, test
the PD bit. If the PD bit is set, the
SLEEP
instruction
was executed as a
NOP
.
To ensure that the WDT is cleared, a
CLRWDT
instruction
should be executed before a
SLEEP
instruction.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PIC16F818-E/ML 功能描述:8位微控制器 -MCU 1.75KB 128RAM 16 I/O Ext Temp QFN28 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F818-E/P 功能描述:8位微控制器 -MCU 1.75KB 128RAM 16 I/O Ext Temp PDIP18 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F818-E/SO 功能描述:8位微控制器 -MCU 1.75KB 128RAM 16 I/O Ext Temp SOIC18 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F818-E/SS 功能描述:8位微控制器 -MCU 1.75KB 128RAM 16 I/O Ext Temp SSOP20 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F818-E/SS 制造商:Microchip Technology Inc 功能描述:IC 8BIT MCU PIC16F 20MHz SSOP-20 制造商:Microchip Technology Inc 功能描述:IC, 8BIT MCU, PIC16F, 20MHz, SSOP-20
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