參數(shù)資料
型號(hào)： PIC16F818
廠商： Microchip Technology Inc.
英文描述： 18/20-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology(18/20引腳，納瓦技術(shù)增強(qiáng)FLASH微控制器)
中文描述： 18/20-Pin增強(qiáng)型閃存微控制器采用納瓦技術(shù)（18/20引腳，納瓦技術(shù)增強(qiáng)閃存微控制器）
文件頁(yè)數(shù)： 29/164頁(yè)
文件大?。?/td> 3045K
代理商： PIC16F818
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2002 Microchip Technology Inc.
Preliminary
DS39598C-page 27
PIC16F818/819
3.3
Reading Data EEPROM Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD con-
trol bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available in the very next
cycle, in the EEDATA register; therefore, it can be read
in the next instruction (see Example 3-1). EEDATA will
hold this value until another read, or until it is written to
by the user (during a write operation).
The steps to reading the EEPROM data memory are:
1.
Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
Clear the EEPGD bit to point to EEPROM data
memory.
Set the RD bit to start the read operation.
Read the data from the EEDATA register.
2.
3.
4.
EXAMPLE 3-1:
DATA EEPROM READ
3.4
Writing to Data EEPROM Memory
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then, the user must follow a
specific write sequence to initiate the write for each
byte.
The write will not initiate if the write sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment (see Example 3-2).
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt, or poll this bit. EEIF must be
cleared by software.
The steps to write to EEPROM data memory are:
1.
If step 10 is not implemented, check the WR bit
to see if a write is in progress.
Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
Write the 8-bit data value to be programmed in
the EEDATA register.
Clear the EEPGD bit to point to EEPROM data
memory.
Set the WREN bit to enable program operations.
Disable interrupts (if enabled).
Execute the special five instruction sequence:
Write 55h to EECON2 in two steps (first to W,
then to EECON2)
Write AAh to EECON2 in two steps (first to W,
then to EECON2)
Set the WR bit
Enable interrupts (if using interrupts).
Clear the WREN bit to disable program
operations.
10. At the completion of the write cycle, the WR bit
is cleared and the EEIF interrupt flag bit is set
(EEIF must be cleared by firmware). If step 1 is
not implemented, then firmware should check
for EEIF to be set, or WR to clear, to indicate the
end of the program cycle.
2.
3.
4.
5.
6.
7.
8.
9.
EXAMPLE 3-2:
DATA EEPROM WRITE
BANKSEL EEADR
MOVF
MOVWF
; Select Bank of EEADR
;
; Data Memory Address
; to read
; Select Bank of EECON1
ADDR,W
EEADR
BANKSEL EECON1
BCF
BSF
BANKSEL EEDATA
MOVF
EECON1,EEPGD ; Point to Data memory
EECON1,RD
; EE Read
; Select Bank of EEDATA
EEDATA,W
; W = EEDATA
BANKSEL EECON1
; Select Bank of
; EECON1
; Wait for write
; to complete
; Select Bank of
; EEADR
;
; Data Memory
; Address to write
;
; Data Memory Value
; to write
; Select Bank of
; EECON1
BTFSC
GOTO
BANKSEL EEADR
EECON1,WR
$-1
MOVF
MOVWF
ADDR,W
EEADR
MOVF
MOVWF
VALUE,W
EEDATA
BANKSEL EECON1
BCF
EECON1,EEPGD; Point to DATA
; memory
EECON1,WREN ; Enable writes
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
; Disable INTs.
;
; Write 55h
;
; Write AAh
; Set WR bit to
; begin write
; Enable INTs.
BSF
BCF
INTCON,GIE
EECON1,WREN ; Disable writes
R
S
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PIC16F818-E/ML 功能描述:8位微控制器 -MCU 1.75KB 128RAM 16 I/O Ext Temp QFN28 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F818-E/P 功能描述:8位微控制器 -MCU 1.75KB 128RAM 16 I/O Ext Temp PDIP18 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F818-E/SO 功能描述:8位微控制器 -MCU 1.75KB 128RAM 16 I/O Ext Temp SOIC18 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F818-E/SS 功能描述:8位微控制器 -MCU 1.75KB 128RAM 16 I/O Ext Temp SSOP20 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F818-E/SS 制造商:Microchip Technology Inc 功能描述:IC 8BIT MCU PIC16F 20MHz SSOP-20 制造商:Microchip Technology Inc 功能描述:IC, 8BIT MCU, PIC16F, 20MHz, SSOP-20
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