參數(shù)資料
型號: PIC16C715
廠商: Microchip Technology Inc.
英文描述: 8-Bit CMOS Microcontroller with A/D Converter(每個I/O口有25mA驅(qū)動/吸收電流,微控制器)
中文描述: 8位CMOS微控制器與A / D轉(zhuǎn)換器(每個的I / O口有25毫安驅(qū)動/吸收電流,微控制器)
文件頁數(shù): 54/120頁
文件大小: 764K
代理商: PIC16C715
PIC16C715
DS30560A-page 54
Advance Information
1996 Microchip Technology Inc.
8.5
There are four sources of interrupt:
Interrupts
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
The “return from interrupt” instruction,
RETFIE
, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
Interrupt Sources
External interrupt RB0/INT
TMR0 overflow interrupt
PORTB change interrupts (pins RB7:RB4)
A/D Interrupt
Note:
Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial function register PIR1. The corresponding interrupt
enable bit is contained in special function register PIE1,
and the peripheral interrupt enable bit is contained in
special function register INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 8-16).
The latency is the same for one or two cycle instruc-
tions. Individual interrupt flag bits are set regardless of
the status of their corresponding mask bit or the GIE
bit.
FIGURE 8-15: INTERRUPT LOGIC
RBIF
RBIE
T0IF
T0IE
INTF
INTE
GIE
Wakeup
(If in SLEEP mode)
Interrupt to CPU
PEIE
ADIF
ADIE
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