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PIC16C715
DS30560A-page 50
Advance Information
1996 Microchip Technology Inc.
8.4.5
PARITY ERROR RESET (PER)
The PIC16C715 has on-chip parity bits that can be
used to verify the contents of program memory. Parity
bits may be useful in applications in order to increase
overall reliability of a system.
There are two parity bits for each word of Program
Memory. The parity bits are computed on alternating
bits of the program word. One computation is per-
formed using even parity, the other using odd parity. As
a program executes, the parity is verified. The even
parity bit is XOR’d with the even bits in the program
memory word. The odd parity bit is negated and XOR’d
with the odd bits in the program memory word. When
an error is detected, a reset is generated and the PER
flag bit 2 in the PCON register is cleared (logic ‘0’). This
indication can allow software to act on a failure. How-
ever, there is no indication of the program memory
location of the failure in Program Memory. This flag can
only be set (logic ‘1’) by software.
The parity array is user selectable during program-
ming. Bit 7 of the configuration word located at address
2007h can be programmed (read as ‘0’) to disable par-
ity. If left unprogrammed (read as ‘1’), parity is enabled.
8.4.6
TIME-OUT SEQUENCE
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay
has expired. Then OST is activated. The total time-out
will vary based on oscillator configuration and the sta-
tus of the PWRT. For example, in RC mode with the
PWRT disabled, there will be no time-out at all.
Figure 8-9, Figure 8-10, and Figure 8-11 depict time-
out sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 8-10). This is useful for testing purposes or to
synchronize more than one PIC16CXX device operat-
ing in parallel.
Table 8-5 shows the reset conditions for some special
function registers, while Table 8-6 shows the reset con-
ditions for all the registers.
8.4.7
POWER CONTROL/STATUS REGISTER
(PCON)
The power control/status register, PCON (address
8Eh) has four bits. See Figure 4-8 for register.
Bit0 is BOR (Brown-out Reset). BOR is unknown on a
Power-on Reset. It must initially be set by the user and
checked on subsequent resets to see if BOR = ‘0’ indi-
cating that a Brown-out Reset has occurred. The BOR
status bit is a “don’t care” bit and is not necessarily pre-
dictable if the brown-out circuit is disabled (by clearing
the BODEN bit in the Configuration word).
Bit1 is POR (Power-on Reset). It is cleared on a Power-
on Reset and is unaffected otherwise. The user set this
bit following a Power-on Reset. On subsequent resets
if POR is ‘0’, it will indicate that a Power-on Reset must
have occurred.
Bit2 is PER (Parity Error Reset). It is cleared on a Parity
Error Reset and must be set by user software. It will
also be set on a Power-on Reset.
Bit7 is MPEEN (Memory Parity Error Enable). This bit
reflects the status of the MPEEN bit in configuration
word. It is unaffected by any reset of interrupt.
TABLE 8-3:
TIME-OUT IN VARIOUS SITUATIONS
TABLE 8-4:
STATUS BITS AND THEIR SIGNIFICANCE
Oscillator Configuration
Power-up
Brown-out
Wake-up from SLEEP
PWRTE = 0
72 ms + 1024T
72 ms
PWRTE = 1
1024T
—
XT, HS, LP
RC
OSC
OSC
72 ms + 1024T
72 ms
OSC
1024T
OSC
—
PER
POR
BOR
TO
PD
1
x
x
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
x
x
x
x
0
1
1
1
1
1
x
0
1
0
x
x
0
0
u
1
1
x
x
1
x
0
x
1
0
u
0
1
x
x
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Parity Error Reset
Illegal, PER is set on POR
Illegal, PER is set on BOR