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參數(shù)資料
| 型號： | PF48F2P0ZBQ0 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Embedded Memory |
| 中文描述： | 英特爾StrataFlash嵌入式存儲器 |
| 文件頁數(shù)： | 87/102頁 |
| 文件大?。?/td> | 1609K |
| 代理商： | PF48F2P0ZBQ0 |
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1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
87
Figure 42.
Buffer Program Flowchart
Buffer Programming Procedure
Start
Get Next
Target Address
Issue Buffer Prog. Cmd.
0xE8,
Word Address
Read Status Register
at Word Address
Write Buffer
Available
SR[7] =
1 = Yes
Device
Supports Buffer
Writes
Set Timeout or
Loop Counter
Timeout
or Count
Expired
Write Confirm 0xD0
and Word Address
(Note 5)
Yes
No
Buffer Program Data,
Start Word Address
X = 0
0 = No
Yes
Use Single Word
Programming
Abort Buffer
Program
No
X = N
Write Buffer Data,
Word Address
X = X + 1
Write to another
Block Address
Buffer Program Aborted
No
Yes
Yes
Write Word Count,
Word Address
Suspend
Program
Loop
Read Status Register
(Note 7)
Is BP finished
SR[7] =
Full Status
Check if Desired
Program Complete
Suspend
Program
1=Yes
0=No
Yes
No
Issue Read
Status Register
Command
No
1. Word count value on D[7:0] is loaded into the word count
register. Count ranges for this device are N = 0x00 to 0x1F.
2. The device outputs the Status Register when read.
3. Write Buffer contents will be programmed at the issued word
address.
4. Align the start address on a Write Buffer boundary for
maximum programming performance (i.e., A[4:0] of the Start
Word Address = 0x00).
5. The Buffered Programming Confirm command must be
issued to an address in the same block, for example, the
original Start Word Address, or the last address used during the
loop that loaded the buffer data.
6. The Status Register indicates an improper command
sequence if the Buffer Program command is aborted; use the
Clear Status Register command to clear error bits.
7. The Status Register can be read from any address within
the programming partition.
Full status check can be done after all erase and write
sequences complete. Write 0xFF after the last operation to
place the partition in the Read Array state.
Bus
Operation
Idle
Read
Command
None
None
Write
Buffer Prog.
Setup
Read
None
Idle
None
Comments
Check SR[7]:
1 = WSM Ready
0 = WSM Busy
Status register Data
Addr = Note 7
Data = 0xE8
Addr = Word Address
SR[7] = Valid
Addr = Word Address
Check SR[7]:
1 = Write Buffer available
0 = No Write Buffer available
Write
(Notes 5, 6)
Buffer Prog.
Conf.
Data = 0xD0
Addr = Original Word Address
Write
(Notes 1, 2)
None
Data = N-1 = Word Count
N = 0 corresponds to count = 1
Addr = Word Address
Write
(Notes 3, 4)
None
Data = Write Buffer Data
Addr = Start Word Address
Write
(Note 3)
None
Data = Write Buffer Data
Addr = Word Address
O
a
p
0
a
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