參數(shù)資料
型號(hào)： PF48F2P0ZBQ0
廠商： Intel Corp.
英文描述： Intel StrataFlash Embedded Memory
中文描述： 英特爾StrataFlash嵌入式存儲(chǔ)器
文件頁(yè)數(shù)： 61/102頁(yè)
文件大?。?/td> 1609K
代理商： PF48F2P0ZBQ0
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
61
11.0
Programming Operations
The device supports three programming methods: Word Programming (40h/10h), Buffered
Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h, D0h). See
Section
9.0, “Device Operations” on page 48
for details on the various programming commands issued to
the device. The following sections describe device programming in detail.
Successful programming requires the addressed block to be unlocked. If the block is locked down,
WP# must be deasserted and the block must be unlocked before attempting to program the block.
Attempting to program a locked block causes a program error (SR[4] and SR[1] set) and
termination of the operation. See
Section 13.0, “Security Modes” on page 69
for details on locking
and unlocking blocks.
The Intel StrataFlash Embedded Memory (P30) is segmented into multiple Programming
Regions. Programming Regions are made up of 8 or 16 blocks depending on the density. The 64-
and 128-Mbit devices have 8 blocks per Programming Region, while the 256-Mbit has 16 blocks in
each Programming Region (see
Table 26
). See
Section 4.4, “Memory Maps” on page 24
for
address ranges of each Programming Region per density.
Execute in Place (XIP) is defined as the ability to execute code directly from the flash memory.
XIP applications must partition the memory such that code and data are in separate programming
regions (see
Table 26, “Programming Regions per Device” on page 61
). Each Programming
Region should contain only code or data, and not both. The following terms define the difference
between code and data. System designs must use these definitions when partitioning their code and
data for the P30 device.
11.1
Word Programming
Word programming operations are initiated by writing the Word Program Setup command to the
device (see
Section 9.0, “Device Operations” on page 48
). This is followed by a second write to the
device with the address and data to be programmed. The device outputs Status Register data when
read. See
Figure 40, “Word Program Flowchart” on page 85
. V
PP
must be above V
PPLK
, and within
the specified V
PPL
min/max values (nominally 1.8 V).
Table 26.
Programming Regions per Device
Device Density
Number of blocks per
Programming Region
Number of Programming
Regions per Device
64-Mbit
8 blocks
8
128-Mbit
8 blocks
16
256-Mbit
16 blocks
16
512-Mbit
16 blocks
32
1-Gbit
16 blocks
64
Code :
Execution code ran out of the flash device on a continuous basis in the system.
Data :
Information periodically programmed into the flash device and read back (e.g.
execution code shadowed and executed in RAM, pictures, log files, etc.).
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參數(shù)描述
PF48F2P0ZT00 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel StrataFlash Embedded Memory
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