參數(shù)資料
型號: PF48F2P0ZBQ0
廠商: Intel Corp.
英文描述: Intel StrataFlash Embedded Memory
中文描述: 英特爾StrataFlash嵌入式存儲器
文件頁數(shù): 60/102頁
文件大?。?/td> 1609K
代理商: PF48F2P0ZBQ0
1-Gbit P30 Family
April 2005
60
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
boundary, the worst case output delay is one clock cycle less than the first access Latency Count.
This delay can take place only once, and doesn’t occur if the burst sequence does not cross a
device-row boundary. WAIT informs the system of this delay when it occurs.
10.3.9
Burst Length
The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the
flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word.
Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see
Table 25, “Burst Sequence Word Ordering” on page 59
). When a burst cycle begins, the device
outputs synchronous burst data until it reaches the end of the “burstable” address space.
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PF48F2P0ZT00 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory
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