參數(shù)資料
型號： PEF2015
廠商： SIEMENS A G
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Mini IOM-2 Controller MICO
中文描述： SPECIALTY TELECOM CIRCUIT, PDSO28
文件頁數(shù)： 57/84頁
文件大小： 1568K
代理商： PEF2015
PEF 2015
Registers Summary
Semiconductor Group
57
12.97
4.2.4.6
Access in demultiplexed
μ
P-interface mode:
Synchronous Transfer Transmit Address Register B (SAXB)
read/write
address: 8
H
OMDR:RBS = 0
address: 10
H
Access in multiplexed
μ
P-interface mode:
Reset value: xx
H
read/write
The SAXB-register specifies for synchronous transfer channel B to which output
interface and time slot the serial data contained in the STDB-register is sent.
ISXB
Interface Select Transmit for channel B.
0…selects the PCM-interface as the output interface for synchronous
channel B.
1…selects the CFI-interface as the output interface for synchronous
channel B.
μ
P-Transfer Transmit Address for channel B; selects the port and time slot
number at the interface selected by ISXB according to
tables 3
and
4
:
MTXB6..0 = MA6..0.
MTXB6..0
4.2.4.7
Access in demultiplexed
μ
P-interface mode:
Synchronous Transfer Control Register (STCR)
read/write
address: 09
H
OMDR:RBS = 0
Access in multiplexed
μ
P-interface mode:
Reset value: 00xxxxxx
B
read/write
address: 12
H
The STCR-register bits are used to enable or disable the synchronous transfer utility and
to determine the sub time slot bandwidth and position if a PCM-interface time slot is
involved.
TAE, TBE
Transfer Channel A (B) Enable.
1… enables the
μ
P transfer of the corresponding channel.
0… disables the
μ
P transfer of the corresponding channel.
bit 7
bit 0
MTXB0
ISXB
MTXB6
MTXB5
MTXB4
MTXB3
MTXB2
MTXB1
bit 7
bit 0
CTA0
TBE
TAE
CTB2
CTB1
CTB0
CTA2
CTA1
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