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參數(shù)資料
| 型號(hào)： | PEF2015 |
| 廠商： | SIEMENS A G |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Mini IOM-2 Controller MICO |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 文件頁(yè)數(shù)： | 45/84頁(yè) |
| 文件大?。?/td> | 1568K |
| 代理商： | PEF2015 |
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PEF 2015
Registers Summary
Semiconductor Group
45
12.97
4.2.2.5
Access in demultiplexed
μ
P-interface mode:
Configurable Interface Bit Shift Register (CBSR)
read/write
address: A
H
OMDR:RBS = 1
Access in multiplexed
μ
P-interface mode:
Reset value: 00
H
read/write
address: 34
H
SFSC
Shift FSC
0...default (behaviour like EPIC-1 PEB 2055)
1...with double clock rate the FSC input is delayed by one CFI clock cycle
(IOM-2 compatibility)
If the bit CBSR:SFSC is set the internal FSC will be delayed by one DCL
clock cycle. This enables synchronization in double clock mode with the
rising DCL edge according to IOM-2. The position of the data bit can now be
adjusted using the CFI bit shift functionality as described below.
CFI-Downstream bit Shift 2..0.
From the zero offset bit position (CBSR = 20
H
) the CFI-frame (downstream
and upstream) can be shifted by up to 6 bits to the left (within the time slot
number TSN programmed in CTAR) and by up to 2 bits to the right (within the
previous time slot TSN - 1) by programming the CBSR:CDS2..0 bits:
CDS2..0
The bit shift programmed to CBSR:CDS2..0 affects both the upstream and
downstream frame position in the same way.
CFI-Upstream bit Shift 3..0.
These bits shift the upstream CFI-frame relative to the downstream frame by
up to 15 bits. For CUS3..0 = 0000, the upstream frame is aligned with the
downstream frame (no bit shift).
CUS3..0
bit 7
SFSC
bit 0
CUS0
CDS2
CDS1
CDS0
CUS3
CUS2
CUS1
CBSR:CDS2..0
000
001
010
011
100
101
110
111
Time Slot No.
TSN - 1
TSN - 1
TSN
TSN
TSN
TSN
TSN
TSN
Bit No.
1
0
7
6
5
4
3
2
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