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參數(shù)資料
| 型號： | PEF2015 |
| 廠商： | SIEMENS A G |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Mini IOM-2 Controller MICO |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 文件頁數(shù)： | 28/84頁 |
| 文件大?。?/td> | 1568K |
| 代理商： | PEF2015 |
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PEF 2015
Operational Description
Semiconductor Group
28
12.97
Synchronous Transfer
For two channels, all switching paths of
figure 8
can also be realized using Synchronous
Transfer. The working principle is that the
μ
P specifies an input time slot (source) and an
output time slot (destination). Both source and destination time slots can be selected
independently from each other at either the PCM- or CFI-interfaces. In each frame, the
MICO first transfers the serial data from the source time slot to an internal data register
from where it can be read and if required overwritten or modified by the
μ
P. This data is
then fed forward to the destination time slot.
Chapter 8
of the EPIC Application Manual 10.92 provides examples of such transfers.
3.4.4
Special Functions
Hardware Timer
The MICO provides one hardware timer which continuously interrupts the
μ
P after a
programmable time period. The timer period can be selected in the range of 250
μ
s up
to 32 ms in multiples of 250
μ
s. Beside the interrupt generation, the timer can also be
used to determine the last look period for 6 and 8-bit signaling channels on IOM-2 and
SLD-interfaces and for the generation of an FSC-multiframe signal (see
chapter 9.1
of
the EPIC Application Manual 10.92).
Power and Clock Supply Supervision
The Connection Memory CM is supervised to data falsfication due to clock or power
failure. If such an inappropriate clocking or power failure occurs, the
μ
P is requested to
reinitialize the device.
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