參數(shù)資料
型號： PEF2015
廠商： SIEMENS A G
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Mini IOM-2 Controller MICO
中文描述： SPECIALTY TELECOM CIRCUIT, PDSO28
文件頁數(shù)： 25/84頁
文件大?。?/td> 1568K
代理商： PEF2015
PEF 2015
Operational Description
Semiconductor Group
25
12.97
Note that the time slot selections in upstream direction are completely independent of
the time slot selections in downstream direction.
CFI – PCM Time Slot Assignment
Switching paths 1 and 2 of
figure 8
can be realized for a total number of up to 128
channels per path, i.e. up to 128 time slots in upstream and up to 128 time slots in
downstream direction. To establish a connection, the
μ
P writes the addresses of the
involved CFI and PCM time slots to the control memory. The actual transfer is then
carried out frame by frame without further
μ
P-intervention.
The switching paths 5 and 6 can be realized by programming time slot assignments in
the control memory. The total number for such loops is limited to the number of available
time slots at the respective opposite interface, i.e. looping back a time slot from CFI to
CFI requires a spare upstream PCM time slot and looping back a time slot from PCM to
PCM requires a spare downstream and upstream CFI time slot.
Time slot switching is always carried out on 8-bit time slots, the actual position and
number of transferred bits can however be limited to 4-bit or 2-bit sub time slots within
these 8-bit time slots. On the CFI-side, only one sub time slot per 8-bit time slot can be
switched, whereas on the PCM-interface up to 4 independent sub time slots can be
switched.
Examples are given in
section 4
of the EPIC Application Manual 10.92.
Sub Time Slot Switching
Sub time slot positions at the PCM-interface can be selected at random, i.e. each single
PCM time slot may contain any mixture of 2- and 4-bit sub time slots. A PCM time slot
may also contain more than one sub time slot. On the CFI however, two restrictions must
be observed:
– Each CFI time slot may contain one and only one sub time slot.
– The sub-slot position for a given bandwidth within the time slot is fixed on a per port
basis and therefore on a per device basis.
For more detailed information on sub-channel switching please refer to
chapter 5.2
of
the EPIC-1 Application Manual 10.92.
μ
P-Transfer
Switching paths 3 and 4 of
figure 8
can be realized for all available time slots. Path 3
can be implemented by defining the corresponding CFI time slots as "
μ
P-channels" or
as "pre-processed channels".
Each single time slot can individually be declared as
"
μ
P-channel"
. If this is the case,
the
μ
P can write a static 8-bit value to a downstream time slot which is then transmitted
repeatedly in each frame until a new value is loaded. In upstream direction, the
μ
P can
read the received 8-bit value whenever required, no interrupts being generated.
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