參數(shù)資料
型號(hào): PCF50732H
廠商: NXP SEMICONDUCTORS
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Baseband and audio interface for GSM
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP48
封裝: PLASTIC, LQFP-48
文件頁數(shù): 40/64頁
文件大小: 322K
代理商: PCF50732H
1999 May 03
40
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
13.3.4
ADD
INSTRUCTION
The ADD (Add to accumulator) instruction is used to add data to the VSP’s accumulator. Flags affected are
EQ0 and EQ1.
Table 37
ADD instruction
13.3.5
SUB
INSTRUCTION
The SUB (Subtract from accumulator) instruction is used to subtract data from the VSP’s accumulator. Flags affected
are EQ0 and EQ1.
Table 38
SUB instruction
13.3.6
MUL
INSTRUCTION
The MUL (Multiply with accumulator) instruction is used to multiply data with the VSP’s accumulator. Flags affected are
EQ0 and EQ1. The second operand of the multiplication is restricted to 16-bit; e.g. R(r.a.).
Table 39
MUL instruction
15 14 13 12 11 10 9 8
7
6
5
4
3
2
1
0
OPERATION
A + coeff
A
A + R(r.a.)
A
A + R(r.a. + I)
A ADD i <r.a.>
ASSEMBLER
NAME
0
0
0
1
1
1
0
0
0
1
0
0
coefficient
ADD c <coeff> add coefficient
ADD r <r.a.>
0
0
0
0
0 X X X
1 X X X
register address
register address
add register
add register
indexed
add port
add integer
add index
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0 X X X X X X port number A + P(p.n.)
A
1
small integer
0 X X X X X X
X
ADD p <p.n.>
ADD s <s.i.>
ADD x
A + s.i.
A
A + I
A
X
X
15 14 13 12 11 10 9 8
7
6
5
4
3
2
1
0
OPERATION
A
coeff
A
ASSEMBLER
NAME
0
1
1
1
coefficient
SUB c <coeff> subtract
coefficient
subtract register
subtract register
indexed
subtract port
subtract integer
subtract index
0
0
1
1
1
1
0
0
0
0
0
0
0 X X X
1 X X X
register address
register address
A
R(r.a.)
A
A
R(r.a. + I)
A SUB i <r.a.>
SUB r <r.a.>
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0 X X X X X X port number A
P(p.n.)
A
1
small integer
0 X X X X X X
X
SUB p <p.n.>
SUB s <s.i.>
SUB x
A
s.i.
A
A
I
A
X
X
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
OPERATION
A
×
coeff
A
ASSEMBLER
NAME
1
0
0
1
coefficient
MUL c <coeff> multiply
coefficient
multiply register
multiply register
indexed
multiply port
multiply integer
multiply index
1
1
0
0
0
0
0
0
0
0
0
0
0 X X X
1 X X X
register address
register address
A
×
R(r.a.)
A
A
×
R(r.a. + I)
A MUL i <r.a.>
MUL r <r.a.>
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0 X X X X X X
1
0 X X X X X X
port number A
×
P(p.n.)
A
small integer
X
X
MUL p <p.n.>
MUL s <s.i.>
MUL x
A
×
s.i.
A
A
×
I
A
X
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