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參數(shù)資料
| 型號： | PCF50732H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Baseband and audio interface for GSM |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 32/64頁 |
| 文件大?。?/td> | 322K |
| 代理商： | PCF50732H |
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1999 May 03
32
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
12.3.8
P
OWER CONTROL REGISTER
The Power control register is used to control power-up and power-down of the different sections of the device. Changing
the power status is accomplished by addressing the device as shown in Table 26 and setting bit 0 (= a) according to the
required state:
a = 0
→
power-down
a = 1
→
power-up.
Setting the baseband RX or TX flag is functionally equivalent to setting RXON or TXON respectively (logical
OR function). The CSI is also accessible when the band gap is powered down. Therefore no reset is required to power-up
after total power-down.
Table 26
Power control register (address 1100 and subaddresses)
FUNCTION
SUBADDRESS
VALUE
DEFAULT
11
(s3)
10
(s2)
9
(s1)
8
(s0)
7
6
5
4
3
2
1
0
VALUE
STATUS
AUXDAC1
AUXDAC2
AUXDAC3
Voice band transmit
Voice band receive
V
ref
Baseband receive
Baseband transmit
Complete device
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
1
0
1
1
0
0
1
0
0
1
1
0
1
0
1
0
0
1
1
don’t care
a
a
a
a
a
a
a
a
a
0
1
0
0
0
1
0
0
1
off
on
off
off
off
on
off
off
on
12.3.9
RAM
INTERFACE REGISTER
The RAM interface register is a general purpose
communication channel between the serial interface CSI
and the voice band signal processor. None of the
processor registers have default values.
The Voice band control register is used to communicate
with the voice band signal processor. Register functions
with subaddress ‘00’ to ‘11’ can be used to program the
Instruction RAM (IRAM) when the voice band processor is
not running, i.e. when voice band receive and transmit
sections are both powered down.
The IRAM registers are used to write into the voice band
instruction RAM.
Normal operation is to write an address into the VSP
instruction RAM program counter and write low and high
bytes of the 16-bit instructions into their respective
locations. No auto-increment is foreseen, i.e. the address
register must be updated by the user. Writing to the IRAM
is only possible when voice band transmit and receive
sections are both powered off. If this is not the case write
actions are ignored.
Reading back from the IRAM is not straightforward due to
the need for an extra clock pulse when accessing RAMs;
when reading back the contents of RAM locations 1, 2, 3
and 4 actual output is ‘undefined’ as 1, 2, 3, etc.
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