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參數(shù)資料
| 型號(hào)： | PCF50732H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Baseband and audio interface for GSM |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 12/64頁 |
| 文件大小： | 322K |
| 代理商： | PCF50732H |
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1999 May 03
12
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
9.3.2.2
Power ramping controller
The PCF50732 fully supports all multislot modes which do
not require full duplex operation or more than two
consecutive transmit bursts. In this specification double
burst mode is used for all supported multislot modes while
single burst mode supports the normal GSM modes.
The power ramping controller drives the power amplifier
output envelope.
In each transmit (TX) burst one ramp-up and one
ramp-down will be carried out. In multislot mode one
intermediate ramp will be carried out in addition to ramp-up
and ramp-down. Each ramp consists of 16 discrete step
values that are sent to the DAC3. Each step’s duration is
2 quarterbits which translates into 8-bit long ramps.
The DAC3 output is in 3-state whenever it is powered
down. The ramping step values are stored in a 64
×
10-bit
RAM as shown in Table 2.
In order to initialize AUXDAC3 it is necessary to write into
the RAM all 32 (or 48 in multislot mode) DAC3 output
values. Filling the RAM is normally done by writing a
logic 0 to the address sub-register of the Burst control
register, after which 32 or 48 values, depending on
multislot mode, can be written into the data sub-register of
the Burst control register. Writing to the DAC3 RAM is only
possible when the DAC3 is powered off.
Total number of CSI-accesses is therefore 33 for a normal
burst and 49 for a double burst.
An autoincrement feature will store these data into the
correct RAM positions.
The value after power-up of DAC3 will always be equal to
the value of RAM location 47.
AUXDAC3 timing is controlled by the Burst control
register. This contains the following sub-registers:
The
RU register
containing the delay in number of
quarterbit cycles from the assertion of TXON to the start
of the power-up ramping; default value is 0
The
RM register
containing the delay in number of
quarterbit cycles from the assertion of TXON to the start
of the intermediate power ramp; default value is 0. RM
is only used in case of multislot mode
The
RD register
containing the delay in number of
quarterbit cycles from the assertion of TXON to the start
of the power-down ramping; default value is 0
DAC3 burst RAM address register
DAC3 burst RAM data register
Single/double burst mode register: normal mode or
multislot mode selection flag.
After TXON goes HIGH and a time equal to RU quarterbit
periods has elapsed, power ramp-up is done.
After a time period equal to RD quarterbits has elapsed
power ramp-down is initiated.
The AUXDAC3 output is also shown in Fig.4.
Values for RU (ramp-up) and RD (ramp-down) can be set
in the Burst control register of the control serial interface.
RD must be greater than RU + 32. RU and RD range
from 0 to 4000 QB (quarterbit). The register offers the
possibility to enter codes up to 4095.
The GMSK modulator is active for a period of 2 clock
cycles after the ramp-down or for the length of the TXON
burst, whichever is longer.
Multislot (high speed switched data mode) can be selected
by setting the appropriate bit in the Burst control register.
In multislot mode an intermediate ramping step is done.
This intermediate step is started after a time period equal
to RM quarterbits has elapsed. A value for RM
(intermediate ramp) is also set using the Burst control
register. The following conditions must be true:
RU + 32 < RM and RM + 32 < RD.
Table 2
AUXDAC3 RAM contents
Table 3
Power ramping timing characteristics
Note
1.
QB: Quarterbit, usually referred to the time needed for
one quarter of a GSM baseband bit, i.e. a frequency of
1
12
×
13 MHz.
RAM ADDRESS
DATA
0 to 15
16 to 31
32 to 47
48 to 64
ramp-up data
intermediate ramp data
ramp-down data
not used
SYMBOL
VALUE
COMMENTS
(1)
t
0
t
ru
t
im
t
rd
t
rup
, t
rim
, t
rdo
12t
1
RU register
RM register
RD register
32t
0
one quarterbit (QB)
0 to 4000 QB
RU + 32 to 4000 QB
RM + 32 to 4000 QB
8 bits; 32 QB
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