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參數(shù)資料
| 型號(hào)： | PCF50732H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Baseband and audio interface for GSM |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁(yè)數(shù)： | 37/64頁(yè) |
| 文件大?。?/td> | 322K |
| 代理商： | PCF50732H |
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1999 May 03
37
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
13.2
VSP assembler language
The stack for return addresses is only one entry deep which means that nesting of subroutines is not possible.
Table 30
VSP instruction set
X = don’t care during a read/or write access. For the description of the bit symbols see notes 1 to 8.
Notes
1.
2.
3.
4.
5.
6.
7.
8.
c11 to c0 denotes a 12-bit twos complement coefficient between
1 and +1.
m3 to m0 denotes a 4-bit instruction mode descriptor.
f2 to f0 denotes a 3-bit flag descriptor.
a8 to a0 denotes a 9-bit address.
i5 to i0 denotes a 6-bit index register value.
a8 to a0 denotes a 9-bit address.
X is a don’t care bit.
im2 to im0 denotes a 3-bit instruction mode descriptor for the IDX operator.
MNEMONIC
INSTRUCTION
I3 I2 I1
I0
D11 D10
D9
D8 D7 D6 D5 D4 D3 D2 D1 D0
LDA
Load accumulator
0
0
0
m3
m3
0
1
m3
m3
m3
m3
m3
m3
0
1
0
1
c11
m2
m2
X
c11
m2
c11
m2
c11
m2
f2
f2
f2
f2
c10
m1
m1
X
c10
m1
c10
m1
c10
m1
f1
f1
f1
f1
c9
m0
m0
X
c9
m0
c9
m0
c9
m0
f0
f0
f0
f0
c8
d8
X
X
c8
d8
c8
d8
c8
d8
a8
a8
a8
a8
c7
d7
X
X
c7
d7
c7
d7
c7
d7
a7
a7
a7
a7
c6
d6
X
X
c6
d6
c6
d6
c6
d6
a6
a6
a6
a6
c5
d5
d5
X
c5
d5
c5
d5
c5
d5
a5
a5
a5
a5
c4
d4
d4
X
c4
d4
c4
d4
c4
d4
a4
a4
a4
a4
c3
d3
d3
X
c3
d3
c3
d3
c3
d3
a3
a3
a3
a3
c2
d2
d2
X
c2
d2
c2
d2
c2
d2
a2
a2
a2
a2
c1
d1
d1
X
c1
d1
c1
d1
c1
d1
a1
a1
a1
a1
c0
d0
d0
X
c0
d0
c0
d0
c0
d0
a0
a0
a0
a0
STO
RTN
ADD
Store accumulator
Return from subroutine
Add to accumulator
0
0
0
0
0
1
1
1
0
SUB
Subtract from
accumulator
0
1
1
MUL
Multiply with accumulator
1
0
0
JMFS
JMFC
JSFS
JSFC
Jump if flag set
Jump if flag clear
Jump subroutine if flag set
Jump subroutine if flag
clear
Set/clear flag
Index operations
1
1
1
1
0
0
1
1
1
1
0
0
STF
IDX
1
1
1
1
1
1
0
1
f2
im2
f1
im1
f0
im0
X
X
X
X
X
X
X
i5
X
i4
X
i3
X
i2
X
i1
d0
i0
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