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參數(shù)資料
| 型號： | PCF50732H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Baseband and audio interface for GSM |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 23/64頁 |
| 文件大?。?/td> | 322K |
| 代理商： | PCF50732H |
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1999 May 03
23
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
12 CONTROL SERIAL INTERFACE (CSI)
The Control Serial Interface block is used to set and read
the status bits inside the PCF50732. It is also used to read
data from the auxiliary ADCs and to write data into the
auxiliary DACs. Finally, the block is used to write the power
ramping curve into a 64
×
10-bit static RAM. It should be
noted that only 48 of the 64 addresses can be accessed;
see Table 2.
12.1
The serial interface
A 4-line bidirectional serial interface is used to control the
circuit. It allows access to each register of the control
register block (read and/or write). The 4 lines are:
Data in (CDI)
Data out (CDO)
Clock (CCLK)
Enable (CEN).
Table 8 lists the normal connections to the PCF5087X.
The data sent to or from the device is loaded in bursts
framed by CEN. Clock edges and data bits are ignored
until CEN goes active (LOW). Each data word consists of
21 bits that comprises a 4-bit device address, a 4-bit
register address, a 12-bit data word and a dummy bit; see
Table 9. The 21 bits are transmitted with MSB first.
Figure 5 shows the valid timing for data transmission on
the control interface.
Data is read in from the CDI pin on the rising edge of the
CCLK clock and output on CDO on the falling edge of the
CCLK clock. Data is written into the registers on the rising
edge of CEN.
If the device address is equal to the chip address, the
programmed information on CDI (DB11 to DB00) is loaded
into the addressed register (RA3 to RA0) when CEN
returns inactive HIGH.
The dummy bit in front is needed for compatibility with
older baseband devices.
Reading a register is accomplished by writing the address
of the required register into the read request register.
The next time CEN goes LOW, the requested data will be
shifted out, together with the register and device address.
Table 8
Pin connection of the CSI to the PCF5087X
Table 9
Bit mapping of the 21-bit words
PCF50732
PCF5087X
PIN
I/O
PIN
I/O
CDI
CDO
CCLK
CEN
I
RFDO
RFDI
RFCLK
RFE_N2
O
I
O
O
O
I
I
BIT
CONTENT
DESCRIPTION
00 to 03 ADD0 to ADD3 device address; for the
PCF50732 this is ‘1001’
(= 9 decimal)
register address
data value
don’t care
04 to 07 RA0 to RA3
08 to 19 DB00 to DB11
20
dummy
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