參數(shù)資料
型號: PCF50732H
廠商: NXP SEMICONDUCTORS
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Baseband and audio interface for GSM
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP48
封裝: PLASTIC, LQFP-48
文件頁數(shù): 35/64頁
文件大?。?/td> 322K
代理商: PCF50732H
1999 May 03
35
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
13 VOICE BAND SIGNAL PROCESSOR (VSP)
13.1
Hardware description
The VSP used in the PCF50732 is a 30-bit fixed point VSP
with separate data and instruction areas. The data path
consists of two guard bits, 16 data bits before and 12 data
bits behind the binary point for a total of 30 bits. Twos
complement notation is used inside the data path.
Intermediate results from calculations are stored in a
64
×
30-bit wide data RAM. Data and Programmable Gain
Amplifier (PGA) settings are read in via 7 input ports and
written back into 3 output ports.
The instruction path uses a 16-bit format with the 4 MSBs
designating the opcode and the trailing 12 bits used to
describe the operand. The VSP has 12 major instructions;
some instructions use two opcodes (operation codes). The
addressing range is 9 bits wide, allowing for a total of
512 instructions, which is more than adequate for the filter
types it is intended to calculate. Some room is available for
Built-In Self Test (BIST). The ALU consists of a 30-bit
subtractor, a 30-bit adder and a 30
×
16-bit ‘modified
booth’-type parallel multiplier.
The VSP’s accumulator has built-in overrange checking
and will limit values to their minimum (in case of underflow)
or maximum (in case of overflow) value.
The VSP engine is designed to operate at 4 MIPS on a
8 kHz PCM signal.
All instructions take one clock-cycle to complete. It should
be noted that since the noise shaper operates at a sample
rate of 32 kHz and the voice band filter operates at a
sample rate of 40 kHz it is necessary to transfer 4 samples
to the receive output and to read 5 samples from transmit
input for each frame.
No buffering is foreseen for these samples, which means
that the VSP program is responsible for proper spacing in
time of the input- and output samples. Failure to ensure
proper spacing will result in heavily distorted signals.
Synchronization to the 8 kHz frame-sync signals AFS is
also done under program control. The VSP program must
ensure that noise shaper and FIR filter are properly reset
before actual operation is started.
A VSP-emulator and a VSP-assembler have been written
in order to facilitate program development. The assembler
generates a stream of 16-bit words that need to be loaded
into the instruction RAM. This is done by repeated writes
to the VSP control register. The sequence would be as
follows:
1.
Write address into the VSP instruction RAM program
counter register
2.
Write the upper 8 bits into the VSP instruction RAM
data high-byte register
3.
Write the lower 8 bits into the VSP instruction RAM
data low-byte register.
This sequence should be repeated until the VSP is fully
programmed. Programming can only be done when the
VSP is not active. The VSP program counter will be set to
location 0 and operation starts after enabling voice band
transmit or voice band receive. See also the CSI
description in Chapter 12.
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