參數(shù)資料
型號(hào)： PCF50732H
廠商： NXP SEMICONDUCTORS
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Baseband and audio interface for GSM
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP48
封裝： PLASTIC, LQFP-48
文件頁(yè)數(shù)： 27/64頁(yè)
文件大?。?/td> 322K
代理商： PCF50732H
1999 May 03
27
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
Table 17
Burst control registers value description
12.3.4
AUXADC
CONTROL REGISTER
Table 18
AUXADC control register (address 0100 and subaddresses)
X = don’t care during a read/or write access.
VALUE OF
DESCRIPTION
RU
Value RU, consisting of RU-lo (least significant byte) and RU-hi (most significant byte), is the delay
measured in quarterbits (
1
12
MCLK) between the rising edge of TXON and the start of the ramp-up on
AUXDAC3. After this delay, the first 16 values of the AUXDAC3 RAM are sent to AUXDAC3. Shifting out
is done at
1
24
MCLK.
Value RM, consisting of RM-lo (least significant byte) and RM-hi (most significant byte), is the delay
measured in quarterbits between the rising edge of TXON and the start of the intermediate ramp in a
double burst ramp. The RM value is only used in multislot mode. RM must be greater than RU + 32.
Value RD, consisting of RD-lo (least significant byte) and RD-hi (most significant byte), is the delay
measured in quarterbits between the rising edge of TXON and the start of the ramp-down on AUXDAC3.
RD must be greater than RU + 32, or in case of multislot mode, greater than RM + 32.
Value BIEN0, consisting of BIEN0-lo (least significant byte) and BIEN0-hi (most significant byte), is the
delay measured in quarterbits between the rising edge of TXON and the falling edge of BIEN.
Value BIEN1, consisting of BIEN1-lo (least significant byte) and BIEN1-hi (most significant byte), is the
delay measured in quarterbits between the rising edge of TXON and the rising edge of BIEN. BIEN1
must be greater than BIEN0.
RM
RD
BIEN0
BIEN1
FUNCTION
SUBADDRESS
VALUE
11
(s2)
10
(s1)
9
(s0)
8
7
6
5
4
3
2
1
0
AUXADC conversion delay
value register
AUXADC flag register
AUXADC offset value
register
I channel offset value
register
Q channel offset value
register
Offset trigger register
0
0
0
X
X
b6
b5
b4
b3
b2
b1
b0
0
1
0
0
1
0
X
Qoff
Ioff
9-bit signed offset compensation value
auxoff
flag 4
flag 3
flag 2
flag 1B flag 1A
1
0
1
9-bit signed offset compensation value
1
1
0
9-bit signed offset compensation value
1
1
1
X
X
X
X
X
X
Q-off
I-off
Aux
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