參數(shù)資料
型號: PCA9698
廠商: NXP Semiconductors N.V.
英文描述: 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
中文描述: 40位調(diào)頻I2C總線先進(jìn)的I / O復(fù)位,光電和INT端口
文件頁數(shù): 8/47頁
文件大?。?/td> 214K
代理商: PCA9698
PCA9698_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 19 July 2006
8 of 47
Philips Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
7.2 Alert response, GPIO All Call and Device ID addresses
Three other different addresses can be sent to the PCA9698.
Alert Response address: allows to perform an ‘SMBus Alert’ operation as defined in
the SMBus specification. This address is always used to perform a Read operation.
See
Section 7.11 “SMBus Alert output (SMBALERT)”
for more information.
GPIO All Call address: allows to program several Advanced GPIO devices at the
same time. This address is always used to perform a Write operation. See
Section 7.6
“GPIO All Call”
for more information.
Device ID address: allows to read ID information from the device (manufacturer, part
identification, revision). See
Section 7.5 “Device ID - PCA9698 ID field”
for more
information.
7.3 Command register
Following the successful acknowledgement of the slave address + R/W bit, the bus
master will send a byte to the PCA9698, which will be stored in the Command register.
The lowest 6 bits are used as a pointer to determine which register will be accessed.
Registers are divided into 2 categories: 5-bank register category, and 1-bank register
category.
Only a command register code with the 7 least significant bits equal to the 28 allowable
values as defined in
Table 3 “Register summary”
will be acknowledged. Reserved or
undefined command codes will not be acknowledged. At power-up, this register defaults
to 80h, with the AI bit set to ‘1’, and the lowest 7 bits set to ‘0'.
During a write operation, the PCA9698 will acknowledge a byte sent to the OP, PI, IOC,
MSK, OUTCONF, ALLBNK, and MODE registers, but will not acknowledge a byte sent to
the IPx registers since these are read-only registers.
Fig 6.
Alert Response address
Fig 7.
GPIO All Call address
Fig 8.
Device ID address
1
002aab938
0
0
0
1
1
0
0
R/W
002aab939
1
1
0
1
1
1
0
0
R/W
R/W
002aab940
1
1
1
1
1
0
0
Fig 9.
Command register
0
002aab941
1
0
0
0
0
0
0
D0
AI
D5
D4
D3
D2
D1
register number
Auto-Increment
default at power-up
or after RESET
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