參數(shù)資料
型號(hào)： PCA9502
廠商： NXP Semiconductors N.V.
英文描述： 8-bit I/O expander with I2C-bus/SPI interface
中文描述： 8位I / O擴(kuò)展接口與I2C-bus/SPI
文件頁(yè)數(shù)： 8/25頁(yè)
文件大?。?/td> 125K
代理商： PCA9502
PCA9502_3
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 13 October 2006
8 of 25
NXP Semiconductors
PCA9502
8-bit I/O expander with I
2
C-bus/SPI interface
A slave receiver must generate an acknowledge after the reception of each byte, and a
master must generate one after the reception of each byte clocked out of the slave
transmitter.
There is an exception to the ‘a(chǎn)cknowledge after every byte’ rule. It occurs when a master
is a receiver: it must signal an end of data to the transmitter by
not
signalling an
acknowledge on the last byte that has been clocked out of the slave. The acknowledge
related clock, generated by the master should still take place, but the SDA line will not be
pulled down. In order to indicate that this is an active and intentional lack of
acknowledgement, we shall term this special condition as a ‘negative acknowledge’.
9.2 Addressing and transfer formats
Each device on the bus has its own unique address. Before any data is transmitted on the
bus, the master transmits on the bus the address of the slave to be accessed for this
transaction. A well-behaved slave with a matching address, if it exists on the network,
should of course acknowledge the master's addressing. The addressing is done by the
first byte transmitted by the master after the START condition.
An address on the network is seven bits long, appearing as the most significant bits of the
address byte. The last bit is a direction (R/W) bit. A ‘0’ indicates that the master is
transmitting (write) and a ‘1’ indicates that the master requests data (read). A complete
data transfer, comprised of an address byte indicating a ‘write’ and two data bytes is
shown in
Figure 8
.
Fig 6.
Data transfer on the I
2
C-bus
S
P
SDA
SCL
MSB
0
1
6
7
8
0
1
2 to 7
8
ACK
ACK
002aab012
START
condition
STOP
condition
acknowledgement signal
from receiver
byte complete,
interrupt within receiver
clock line held LOW
while interrupt is serviced
Fig 7.
Acknowledge on the I
2
C-bus
S
0
1
6
7
8
002aab013
data output
by transmitter
data output
by receiver
SCL from master
START
condition
transmitter stays off of the bus
during the acknowledge clock
acknowledgement signal
from receiver
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PCA9502BS,128 功能描述:接口-I/O擴(kuò)展器 8-BITI/O EXPDR RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel
PCA9502BS,151 功能描述:接口-I/O擴(kuò)展器 I/O EXPANDER I2C RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel
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