參數(shù)資料
型號: PCA9502
廠商: NXP Semiconductors N.V.
英文描述: 8-bit I/O expander with I2C-bus/SPI interface
中文描述: 8位I / O擴展接口與I2C-bus/SPI
文件頁數(shù): 15/25頁
文件大?。?/td> 125K
代理商: PCA9502
PCA9502_3
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 13 October 2006
15 of 25
NXP Semiconductors
PCA9502
8-bit I/O expander with I
2
C-bus/SPI interface
[1]
5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 3.8 V steady state voltage
tolerance on inputs and outputs when no supply voltage is present.
13. Dynamic characteristics
[1]
A detailed description of the I
2
C-bus specification, with applications, is given in brochure “The I
2
C-bus and how to use it” This brochure
may be ordered using the code 9398 393 40011.
[2]
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if SDA is held LOW for a
minimum of 25 ms.
I
2
C-bus inputs SCL, CS/A0, SI/A1
V
IH
HIGH-level input voltage
V
IL
LOW-level input voltage
I
L
leakage current
C
i
input capacitance
1.6
-
-
-
5.5
[1]
0.6
10
7
2.0
-
-
-
5.5
[1]
0.8
10
7
V
V
μ
A
pF
input; V
I
= 0 V or 5.5 V
[1]
Table 15.
V
DD
= (2.5 V
±
0.2 V) or (3.3 V
±
0.3 V); T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol
Parameter
Conditions
Static characteristics
…continued
V
DD
= 2.5 V
Min
V
DD
= 3.3 V
Min
Unit
Max
Max
Table 16.
All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
V
DD
= (2.5 V
±
0.2 V) or (3.3 V
±
0.3 V); T
amb
=
40
°
C to +85
°
C; refer to V
IL
and V
IH
with an input voltage of V
SS
to V
DD
.
All output load = 25 pF except SDA output load = 400 pF
[1]
Symbol Parameter
Conditions
I
2
C-bus timing specifications
Standard-mode
I
2
C-bus
Min
0
4.7
Fast-mode
I
2
C-bus
Min
0
1.3
Unit
Max
100
-
Max
400
-
f
SCL
t
BUF
SCL clock frequency
bus free time between a STOP and
START condition
hold time (repeated) START condition
set-up time for a repeated START
condition
set-up time for STOP condition
data hold time
data valid acknowledge time
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
fall time of both SDA and SCL signals
rise time of both SDA and SCL signals
pulse width of spikes that must be
suppressed by the input filter
I
2
C-bus GPIO output valid time
I2C input pin interrupt valid time
I2C input pin interrupt clear time
[2]
kHz
μ
s
t
HD;STA
t
SU;STA
4.0
4.7
-
-
0.6
0.6
-
-
μ
s
μ
s
t
SU;STO
t
HD;DAT
t
VD;ACK
t
VD;DAT
t
SU;DAT
t
LOW
t
HIGH
t
f
t
r
t
SP
4.7
0
-
-
250
4.7
4.0
-
-
-
-
-
0.6
0
-
-
150
1.3
0.6
-
-
-
-
-
μ
s
ns
μ
s
ns
ns
μ
s
μ
s
ns
ns
ns
0.6
0.6
-
-
-
300
1000
50
0.6
0.6
-
-
-
300
300
50
SCL LOW to data out valid
t
d1
t
d4
t
d5
0.5
0.2
0.2
-
-
-
0.5
0.2
0.2
-
-
-
μ
s
μ
s
μ
s
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