參數(shù)資料
型號: PCA9502
廠商: NXP Semiconductors N.V.
英文描述: 8-bit I/O expander with I2C-bus/SPI interface
中文描述: 8位I / O擴(kuò)展接口與I2C-bus/SPI
文件頁數(shù): 4/25頁
文件大?。?/td> 125K
代理商: PCA9502
PCA9502_3
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 13 October 2006
4 of 25
NXP Semiconductors
PCA9502
8-bit I/O expander with I
2
C-bus/SPI interface
[1]
See
Section 7.1 “Hardware reset, Power-On Reset (POR) and software reset”
7.
Functional description
The device interfaces to a host through either I
2
C-bus or SPI interface (selectable through
I2C/SPI pin), and provides the host with eight programmable GPIO pins.
7.1 Hardware reset, Power-On Reset (POR) and software reset
These three reset methods are identical and will reset the internal registers as indicated in
Table 3
.
Table 3
summarizes the state of registers after reset.
Table 4
summarizes the state of hardware pins after reset.
IRQ
12
O
Interrupt (open-drain, active LOW). Interrupt is enabled when
interrupt sources are enabled in the I/O Interrupt Enable register
(IOIntEna). The interrupt condition is the change of state of the
input pins. An external resistor (1 k
for 3.3 V, 1.5 k
for 2.5 V)
must be connected between this pin and V
DD
.
programmable I/O pin
programmable I/O pin
programmable I/O pin
programmable I/O pin
programmable I/O pin
programmable I/O pin
programmable I/O pin
programmable I/O pin
ground
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
V
SS
13
14
15
16
18
19
20
21
10, 17,
23
center
pad
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
V
SS
-
The center pad on the back side of the HVQFN24 package is
metallic and should be connected to ground on the printed-circuit
board.
Table 2.
Symbol
Pin description
…continued
Pin
Type
Description
Table 3.
Register
I/O direction
Registers after reset
Reset state
all bits cleared
I/O interrupt enable
all bits cleared
I/O control
all bits cleared
Table 4.
Signal
I/Os
IRQ
Signals after reset
Reset state
inputs
HIGH by external pull-up
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