參數(shù)資料
型號: PCA9502
廠商: NXP Semiconductors N.V.
英文描述: 8-bit I/O expander with I2C-bus/SPI interface
中文描述: 8位I / O擴展接口與I2C-bus/SPI
文件頁數(shù): 12/25頁
文件大?。?/td> 125K
代理商: PCA9502
PCA9502_3
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 13 October 2006
12 of 25
NXP Semiconductors
PCA9502
8-bit I/O expander with I
2
C-bus/SPI interface
The register read cycle (see
Figure 11
) commences in a similar manner, with the master
sending a slave address with the direction bit set to ‘write’ with a following sub-address.
Then, in order to reverse the direction of the transfer, the master issues a repeated START
followed again by the device address, but this time with the direction bit set to ‘read’. The
data bytes starting at the internal sub-address will be clocked out of the device, each
followed by a master-generated acknowledge. The last byte of the read cycle will be
followed by a negative acknowledge, signalling the end of transfer. The cycle is terminated
by a STOP signal.
White block: host to PCA9502
Grey block: PCA9502 to host
Fig 10. Master writes to slave
S
SLAVE ADDRESS
002aab047
W
A
REGISTER ADDRESS
A
nDATA
A
P
White block: host to PCA9502
Grey block: PCA9502 to host
Fig 11. Master read from Slave
S
SLAVE ADDRESS
002aab048
W
A
REGISTER ADDRESS
A
NA
P
S
SLAVE ADDRESS
R
A
nDATA
A
LAST DATA
Table 12.
Bit
7
6:3
2:1
0
Register address byte (I
2
C-bus)
Name
-
A[3:0]
-
-
Function
not used
internal register select
not used, set to 0
not used
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