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參數(shù)資料
| 型號： | P90CE201AEB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-bit microcontroller |
| 中文描述： | 16-BIT, 24 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 68/77頁 |
| 文件大?。?/td> | 235K |
| 代理商： | P90CE201AEB |
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August 1993
68
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
15.3.4
F
AST
I
2
C-
BUS TIMING
.
Table 58
Fast I
2
C-bus timing.
Notes
1.
A device must internally provide a hold time of at least 300 ns for the SDA signal, referenced to V
IHmin
of the SCL
signal, in order to bridge the undefined region of the falling edge of SCL. The maximum t
HD;DAT
has to be met only if
the device does not stretch the SCL LOW period (t
LOW
).
A fast-mode I
2
C-bus device can be used in a “0-to-100 kbit/s” I
2
C-bus system and then the requirement
t
SU;DAT
> 250 ns must be fulfilled. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. But if such a device stretches the LOW period of the SCL signal, it must output the next data bit
to the SDA line (t
RDmax
+
t
SU;DAT
) = 1000
+
250 = 1250 ns before the SCL line is released according to the existing
“0-to-100 kbit/s” I
2
C-bus specification.
C
b
= Total capacitance value of one bus line in pF.
2.
3.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
f
SCL
t
BUF
t
HD; STA
t
LOW
t
HIGH
t
SU; STA
t
HD; DAT
t
SU; DAT
t
RC
;t
RD
t
FC;
t
FD
t
SU; STO
C
b
SCL clock frequency
bus free time between a STOP and START condition
hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
set-up time (repeated) START
data hold time (note 1)
data set-up time (note 2)
rise time of both SDA and SCL lines (note 3)
fall time of both SDA and SCL lines (note 3)
set-up time for STOP condition
capacitive load of each bus line
0
1300
600
1300
600
600
0
100
(20
+
0.1Cb)
(20
+
0.1Cb)
600
400
900
300
300
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
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