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參數(shù)資料
| 型號(hào)： | P90CE201AEB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-bit microcontroller |
| 中文描述： | 16-BIT, 24 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 6/77頁 |
| 文件大小： | 235K |
| 代理商： | P90CE201AEB |
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August 1993
6
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
4.2
Pin description
Table 1
QFP64 package.
MNEMONIC
TYPE
PIN NO.
FUNCTION
RXD
SDA2
I/O
I/O
1
2
Receive Data.
RXD is the data input for the UART interface.
Serial Data 2
(open drain). SDA2 is the data signal for the second
I
2
C-bus serial interface.
Serial Clock 2
(open drain). SCL2 is the clock signal for the second
I
2
C-bus serial interface.
General Purpose Port
(active HIGH, 3-state). The alternative functions
are as follows. SCL1 is the clock signal for the first I
2
C-bus serial
interface. SDA1 is the data signal for the first I
2
C-bus serial interface.
T1 is the input pin for Timer 1.
SCL2
I/O
3
GP7/SDA1
GP6/SCL1
GP0
GP1
GP2
GP3
GP4
GP5/T1
A23/AP7
to
A16/AP0
A15 to A0
I/O
4
5
6
7
8
9
10
11
12 to 15, 21,
22, 24, 23
I/O
Address Bus.
Upper 8-bits of the address bus (A23 to A16). The unused
address bits can be selected as a quasi-bidirectional port (AP).
O
25, 26, 28, 27,
34, 38, 32, 30,
29, 31, 33, 35,
37, 39, 40, 42
16
17
Address Bus.
Lower 16-bits of the address bus.
XTAL2
XTAL1
O
I
Oscillator output.
Not connected if an external clock generator is used.
Oscillator input.
XTAL1 can also be used as an external clock input if
an external clock generator is used.
Supply voltage.
For internal logic, address bus, data bus, RWN,
CSRAMN, CSROMN, XTAL1 and XTAL2.
Ground.
For internal logic, address bus, data bus, RWN, CSRAMN,
CSROMN, XTAL1 and XTAL2.
Read
(active HIGH)/
Write
(active LOW). This controls the direction of
data flow.
Chip Select ROM
(active LOW). This signal selects external ROM.
Data Bus.
8-bit data bus.
V
DD1
18
V
SS1
19
R/WN
O
20
CSROMN
D0 to D7
O
O
36
44, 46, 48, 49,
47, 45, 43, 41
50
51
52
53
54
55
CSRAMN
V
SS2
V
DD2
RESET
T0
T2
O
I
I
I
Chip Select RAM
(active LOW). This signal enables external RAM.
Ground.
For all other periphery pins (quiet port).
Supply voltage.
For all other periphery pins (quiet port).
Reset
(active HIGH). Input pin for an external reset.
Timer 0.
Input pin for cycle and event counting using Timer 0.
Timer 2.
Input pin for cycle and event counting using Timer 2.
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