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參數(shù)資料
| 型號： | P90CE201AEB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-bit microcontroller |
| 中文描述： | 16-BIT, 24 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 45/77頁 |
| 文件大?。?/td> | 235K |
| 代理商： | P90CE201AEB |
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August 1993
45
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
8.2.3
D
ATA
S
HIFT
R
EGISTER
(SnDAT)
S1DAT is located at address 8000 2001H; S2DAT is located at address 8000 2011H. These two identical registers
contain the serial data to be transmitted or data that has just been received. Bit 7 is transmitted or received first; i.e. data
shifted from right to left. These registers have a default value of 00H.
8.2.4
A
DDRESS
R
EGISTER
(SnADR)
S1ADR resides at address 8000 2003H; S2ADR resides at address 8000 2013H. These two identical 8-bit registers may
be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave
receiver/transmitter. The LSB (GC) is used to determine whether the general call address is recognized. These registers
have a default value of 00H.
Table 38
Description of SnADR bits.
SYMBOL
BIT
FUNCTION
SLA6 to SLA0
GC
SnADR.7 to SnADR.1
SnADR.0
Own slave address
When a logic 0, the general call address is not recognized. When a logic 1,
the general call address is recognized
Fig.27 Data Shift Register (SnDAT).
bit 7
DATA.7
bit 6
DATA.6
bit 5
DATA.5
bit 4
DATA.4
bit 3
DATA.3
bit 2
DATA.2
bit 1
DATA.1
bit 0
DATA.0
Fig.28 Address Register (SnADR).
bit 7
SLA6
bit 6
SLA5
bit 5
SLA4
bit 4
SLA3
bit 3
SLA2
bit 2
SLA1
bit 1
SLA0
bit 0
GC
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