參數(shù)資料
型號(hào)： P90CE201AEB
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 16-bit microcontroller
中文描述： 16-BIT, 24 MHz, MICROCONTROLLER, PQFP64
封裝： PLASTIC, QFP-64
文件頁(yè)數(shù)： 19/77頁(yè)
文件大?。?/td> 235K
代理商： P90CE201AEB
August 1993
19
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
6.2
Interrupt controller
An interrupt controller handles all internal and external
interrupts. It passes the interrupt with the highest level
priority to the CPU.
The following interrupt requests are generated by the
on-chip peripherals.
I
2
C1
I
2
C2
UART receiver
UART transmitter
Timer 2
Timer 1
Timer 0.
The following interrupt requests are sent via external pins.
INTN0 to INTN7
6.2.1
I
NTERRUPT ARBITRATION
The priority level of all interrupts are programmable and
each may be allocated a value between 0 and 7. Level 7
has the highest priority, level 0 disables the corresponding
interrupt source. In the event of interrupt requests of equal
priority level occurring at the same time, then a hardware
mechanism gives the following order.
INTN7
INTN6
INTN5
INTN4
INTN3
INTN2
INTN1
INTN0
Timer 2
Timer 1
Timer 0
UART receiver
UART transmitter
I
2
C2
I
2
C1.
The execution of interrupt routines may be interrupted by
another higher priority level interrupt request (nested
interrupts). In the 68070 mode (SYSCON2.7 = 1), when an
interrupt is serviced by the CPU, the corresponding level is
loaded into the Status Register. This prevents the current
interrupt from getting interrupted by another interrupt
request with the same or lower priority level. If
SYSCON2.7 = 0, priority level 7 will always be loaded into
the Status Register and therefore the current interrupt
cannot be interrupted by any other interrupt request.
6.2.2
A
CKNOWLEDGE AND INTERRUPT VECTORS
When the CPU is ready to service a particular interrupt
request, it initiates an “interrupt acknowledge cycle” in
order to obtain the interrupt vector from the requesting
device. When the device recognizes that its interrupt
request has been accepted it either provides an 8-bit
interrupt vector together with an internal DTACKN signal
(vector mode), or it asserts an internal AVN signal and the
interrupt vector is calculated from the interrupt level.
6.2.3
E
XTERNAL LATCHED INTERRUPTS
INTN7 to INTN0 are 8 external interrupt inputs; each
triggered on the falling edge of the input. Their priority
levels as well as their interrupt vectors are programmable.
As an alternative function INTN7 to INTN0 may be used as
I/O ports. When an interrupt pin is programmed as a port,
the corresponding bit in the Port Control Register LPCRH
(or LPCRL) is used for port I/O. A read from either of these
two registers reads the value from the corresponding bit in
the Port Control Register. A read from the Port Pad Control
Register LPPH (or LPPL) reads the value from the
corresponding port input pin. A write to LPCRH (or LPCRL)
or to LPPH (or LPPL) writes the value to the corresponding
port register, from where it is driven to the corresponding
port pin.
The port function is configured as a quasi-bidirectional
port. A bit is set to input mode by writing a logic 1 to the
corresponding Port Control Register bit. This drives a
“weak” logic 1 to the corresponding output pin, which can
be overwritten by an external signal.
In the following register descriptions “n” represents the
external interrupt number (0 to 7), its associated registers
are identified using the same number.
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