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參數資料
| 型號： | P90CE201AEB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-bit microcontroller |
| 中文描述： | 16-BIT, 24 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數： | 26/77頁 |
| 文件大小： | 235K |
| 代理商： | P90CE201AEB |
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August 1993
26
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
6.4
Reset
The reset input for the P90CE201 is RESET (pin 53). A
Schmitt trigger is used at the input for noise rejection. The
output of the Schmitt trigger is sampled by the reset
circuitry every machine cycle. The internal reset circuitry
has an additional input which is activated by an overflow of
the Watchdog Timer (WDTIM). The On-chip Reset
configuration is shown in Fig.20.
A global reset may be performed by three different
methods:
Applying an external signal to the RESET pin
Automatic Power-on-reset circuitry
Activated by an overflow of the Watchdog Timer.
During the reset operation the CPU and peripherals are
reset. After an internal start-up time, the CPU reads the
reset vectors (the reset vectors are four words long).
Address 000000H is loaded into the Supervisor Stack
Pointer (SSP), and address 000004H is loaded into the
Program Counter (PC). As soon as the SSP and PC have
been loaded, the CPU initializes the Status Register to
interrupt level 7. Instruction execution then starts at the
address indicated by the Program Counter.
6.4.1
E
XTERNAL RESET USING THE RESET PIN
An external reset is accomplished by applying an external
signal to the RESET pin. To ensure that the oscillator is
stable before the controller starts, the external signal must
be held HIGH for at least 100 ms.
6.4.2
A
UTOMATIC
P
OWER
-
ON RESET
Providing the rise time of V
DD
does not exceed 10 ms, an
automatic reset can be obtained by connecting the RESET
pin to V
DD
, via a 2.2
μ
F capacitor. When the power is
switched on, the voltage on the RESET pin is equal to V
DD
minus the capacitor voltage, and decreases from V
DD
as
the capacitor charges through the internal resistor
(R
RESET
) to ground. The larger the capacitor, the more
slowly V
RESET
decreases. V
RESET
must remain above the
lower threshold of the Schmitt trigger long enough to effect
a complete reset. The time required is the oscillator
start-up time, plus 2 machine cycles. The Power-on reset
circuitry is shown in Fig.21.
6.4.3
R
ESET ACTIVATED BY AN OVERFLOW OF THE
W
ATCHDOG
T
IMER
A reset can also be initiated by an overflow of the
Watchdog Timer (see Fig.20). After a reset operation the
Watchdog Timer is disabled.
Note that when the CPU executes a RESET instruction,
the CPU is not affected, only the on-chip peripherals are
reset.
Fig.20 On-chip reset configuration.
MLB007
SCHMITT
TRIGGER
RESET
CIRCUITRY
RESET
on-chip
resistor
Watchdog
timer overflow
Fig.21 Power-on reset circuitry.
handbook, halfpage
VDD
RESET
2.2
μ
F
RRESET
MLB006
P90CE201
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