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| 型號： | P90CE201AEB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-bit microcontroller |
| 中文描述： | 16-BIT, 24 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 46/77頁 |
| 文件大小： | 235K |
| 代理商： | P90CE201AEB |
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August 1993
46
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
8.2.5
I
NTERRUPT REGISTERS
The I
2
C-bus interface contains four registers for the control of I
2
C-bus interrupts. One pair of registers (S1IR and S1IV)
provide independent control of the I
2
C1 interface interrupts; the other pair of registers (S2IR and S2IV) provide
independent control of the I
2
C2 interface interrupts.
In the following register descriptions “n” represents the I
2
C-bus interface number (1 or 2), its associated registers are
identified using the same number.
8.2.6
I
NTERRUPT
R
EGISTERS
(SnIR)
These registers have a default value of XX0X0000
b
.
Table 39
Description of SnIR bits.
Table 40
Selection of interrupt priority level.
SYMBOL
AVN
BIT
FUNCTION
SnIR.7
SnIR.6
SnIR.5
Reserved
Reserved
Autovector. When AVN = 0; the interrupt is an autovectored interrupt and the processor
calculates the appropriate vector from a fixed vector table. AVN = 0 is also the default
value. When AVN = 1; the interrupt is a vectored interrupt and the peripheral must provide
an 8-bit vector number.
Reserved
Pending Interrupt Request. This bit is set to a logic 1 when a valid interrupt request has
been detected. It is automatically reset by the interrupt acknowledge cycle from the CPU.
If PIR = 0, there is no pending interrupt request; this is also the default value. The PIR bit
can also be reset by software by writing a logic 0 to this location.
Interrupt Priority Level. These three bits select the interrupt priority level. See Table 40.
SnIR.4
SnIR.3
PIR
IPL2
IPL1
IPL0
SnIR.2
SnIR.1
SnIR.1
IPL2
IPL1
IPL0
PRIORITY LEVEL
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt inhibited; this is also the default value.
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Fig.29 Interrupt Register (SnIR).
bit 7
bit 6
bit 5
AVN
bit 4
bit 3
PIR
bit 2
IPL2
bit 1
IPL1
bit 0
IPL0
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