參數(shù)資料
型號(hào): P90CE201AEB
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 16-bit microcontroller
中文描述: 16-BIT, 24 MHz, MICROCONTROLLER, PQFP64
封裝: PLASTIC, QFP-64
文件頁數(shù): 55/77頁
文件大?。?/td> 235K
代理商: P90CE201AEB
August 1993
55
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
13 TIMERS
13.1
General
The P90CE201 contains three almost identical, fully
independent 16-bit timers (T0, T1 and T2). In the following
general description of the timer block, “n” represents the
number of the Timer (0, 1 or 2).
Timer n is a 16-bit timer/counter which is formed by the two
8-bit registers TLn and THn. Another pair of registers,
RCAPLn and RCAPHn, form a 16-bit capture register or a
16-bit reload register. The timers can operate either as a
timer or as an event counter. The selection of the clock
source for each timer is done in register SYSCON2 (see
Table 12). The timers have three operation modes.
The differences between the three timers are listed below:
Table 47
Selection of the trigger pulse.
Mode 1:
Mode 2:
mode 3:
Timer/counter in capture mode
Timer/counter in auto-reload mode
Timer/counter in baud rate generator mode
for UART
Timer 0:
Operates in all modes with the internal
frequency of f
XTAL
/2 or f
XTAL
/32.
Timer 0 contains a transition detection
circuit for the external input. The detection
circuitry is controlled by two bits in
SYSCON2; all possible transitions can be
monitored. Table 47 shows the selection of
the trigger pulse.
SYSCON2.3
SYSCON2.2
TRANSITION
0
0
1
0
1
0
no edge detection
rising edge detection
falling edge detection
(default value)
falling and rising edge
detection
1
1
Timer 1:
Operates in all modes with the internal
frequency of f
XTAL
/2 or f
XTAL
/32. Transition
detection for the external input is fixed to
falling edge detection.
Operates in all modes with the internal
frequency of f
XTAL
/2 or BPCLK/4. Transition
detection for the external input is fixed to
falling edge detection.
Timer 2:
13.2
Timer operating modes
The Timer Control Register (TnCON) controls the
selection of the timer operating modes; this is described in
section 13.3.1 Timer Control Register (TnCON).
13.2.1
C
APTURE MODE
In the Capture mode there are two options which are
selected by the EXENn bit in TnCON. If EXENn = 0, then
Timer n is a 16-bit timer/counter which on overflow sets the
Overflow bit TFn. The overflow can be used to generate an
interrupt. If EXENn = 1, then Timer n operates in the same
way as EXENn = 0 but with the additional feature that a
valid transition at the external input Tn causes the current
value in Timer n registers (TLn and THn) to be captured
into registers RCAPLn and RCAPHn, respectively. The
transition at input Tn also causes the EXFn bit in TnCON
to be set; this can also be used to generate an interrupt.
13.2.2
A
UTO
-
RELOAD MODE
In the Auto-reload mode there are two options which are
selected by the EXENn bit in TnCON. If EXENn = 0, then
a Timer n overflow sets the TFn bit and causes the Timer
n registers to be reloaded with the 16-bit value held in
registers RCAPLn and RCAPHn. This 16-bit value is
preset by software. The overflow can be used to generate
an interrupt. If EXENn = 1, then Timer n operates as above
but with the additional feature that a valid transition at the
external input Tn triggers the 16-bit reload and sets the
EXFn bit. The transition can also be used to generate an
interrupt.
13.2.3
B
AUD
R
ATE
G
ENERATOR MODE
The baud rate generator mode for the UART is selected by
RCLKn and/or TCLKn in TnCON. Overflows of Timer n can
be used or generating baud rates for transmit and receive
of the UART in its Modes 1 and 3. See Table 50. The baud
rate generation mode is similar to the auto-reload mode, in
that a rollover in THn causes the Timer n registers to be
reloaded with the 16-bit value held in registers RCAPLn
and RCAPHn, which are preset by software. The baud rate
for the UART is determined by Timer n’s overflow rate as
specified below.
Baud rate
Timer n 16
=
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