參數(shù)資料
型號: P89LPC930
廠商: NXP Semiconductors N.V.
英文描述: 8-bit microcontrollers with two-clock 80C51 core 4 kB/8 kB 3 V Flash with 256-byte data RAM
中文描述: 8位微控制器兩個小時80C51的核心4 KB的/ 8 KB的256 3伏閃存內(nèi)存字節(jié)的數(shù)據(jù)
文件頁數(shù): 48/55頁
文件大?。?/td> 267K
代理商: P89LPC930
Philips Semiconductors
P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 05 — 15 December 2004
48 of 55
9397 750 14472
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until V
DD
has reached its specified level. When system power is removed V
DD
will fall below the
minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout
detect circuit may be required to hold the device in reset when V
DD
falls below the minimum specified operating voltage.
[2]
t
SPIF
Fall time
see Figures
15
,
16
,
17
,
18
SPI outputs (SPICLK, MOSI,
MISO)
SPI inputs (SPICLK, MOSI,
MISO, SS)
-
100
-
100
ns
-
2000
-
2000
ns
Table 9:
V
DD
= 3.0 V to 3.6 V unless otherwise specified.
T
amb
=
40
°
C to +85
°
C for industrial, unless otherwise specified.
[1]
Symbol
Parameter
AC characteristics
…continued
Conditions
Variable clock
Min
f
osc
= 18 MHz
Min
Unit
Max
Max
Fig 15. SPI master timing (CPHA = 0).
tCLCL
tSPICLKH
tSPICLKL
Master LSB/MSB out
Master MSB/LSB out
tSPIDH
tSPIDSU
tSPICLKL
tSPICLKH
tSPIF
tSPIOH
tSPIDV
tSPIR
tSPIDV
tSPIF
tSPIF
tSPIR
tSPIR
SS
SPICLK
(CPOL = 0)
(output)
002aaa156
SPICLK
(CPOL = 1)
(output)
MISO
(input)
MOSI
(output)
LSB/MSB in
MSB/LSB in
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