參數(shù)資料
型號: P89LPC930
廠商: NXP Semiconductors N.V.
英文描述: 8-bit microcontrollers with two-clock 80C51 core 4 kB/8 kB 3 V Flash with 256-byte data RAM
中文描述: 8位微控制器兩個小時80C51的核心4 KB的/ 8 KB的256 3伏閃存內存字節(jié)的數(shù)據(jù)
文件頁數(shù): 32/55頁
文件大小: 267K
代理商: P89LPC930
Philips Semiconductors
P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 05 — 15 December 2004
32 of 55
9397 750 14472
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
The SPI interface has four pins: SPICLK, MOSI, MISO, and SS:
SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and
flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal
is output in the master mode and is input in the slave mode. If the SPI system is
disabled, i.e. SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port
functions.
SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave
device uses its SS pin to determine whether it is selected.
Typical connections are shown in Figures
10
,
11
, and
12
.
Fig 9.
SPI block diagram.
002aaa434
CPU clock
DIVIDER
BY 4, 16, 64, 128
SELECT
CLOCK LOGIC
SPI CONTROL REGISTER
READ DATA BUFFER
8-BIT SHIFT REGISTER
SPI CONTROL
SPI STATUS REGISTER
S
S
W
S
SPI clock (master)
P
S
M
S
M
M
S
MISO
P2.3
MOSI
P2.2
SPICLK
P2.5
SS
P2.4
SPI
interrupt
request
internal
data
bus
S
S
S
M
D
M
C
C
S
S
MSTR
SPEN
clock
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