參數(shù)資料
型號： P89LPC930
廠商： NXP Semiconductors N.V.
英文描述： 8-bit microcontrollers with two-clock 80C51 core 4 kB/8 kB 3 V Flash with 256-byte data RAM
中文描述： 8位微控制器兩個(gè)小時(shí)80C51的核心4 KB的/ 8 KB的256 3伏閃存內(nèi)存字節(jié)的數(shù)據(jù)
文件頁數(shù)： 46/55頁
文件大?。?/td> 267K
代理商： P89LPC930
Philips Semiconductors
P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 05 — 15 December 2004
46 of 55
9397 750 14472
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table 9:
V
DD
= 3.0 V to 3.6 V unless otherwise specified.
T
amb
=
40
°
C to +85
°
C for industrial, unless otherwise specified.
[1]
Symbol
Parameter
AC characteristics
Conditions
Variable clock
Min
7.189
320
f
osc
= 18 MHz
Min
7.189
320
Unit
Max
7.557
520
Max
7.557
520
f
RCOSC
f
WDOSC
internal RC oscillator frequency
internal Watchdog oscillator
frequency
oscillator frequency
clock cycle
CLKLP active frequency
MHz
kHz
f
osc
t
CLCL
f
CLKP
Glitch filter
[2]
0
18
-
8
-
-
-
-
-
-
MHz
ns
MHz
see
Figure 20
55
0
glitch rejection, P1.5/RST pin
signal acceptance, P1.5/RST pin
glitch rejection, any pin except
P1.5/RST
signal acceptance, any pin except
P1.5/RST
External clock
t
CHCX
HIGH time
t
CLCX
LOW time
t
CLCH
rise time
t
CHCL
fall time
Shift register (UART mode 0)
t
XLXL
serial port clock cycle time
t
QVXH
output data set-up to clock rising
edge
t
XHQX
output data hold after clock rising
edge
t
XHDX
input data hold after clock rising
edge
t
DVXH
input data valid to clock rising edge
SPI interface
f
SPI
Operating frequency
3.0 MHz (Slave)
4.5 MHz (Master)
t
SPICYC
Cycle time
-
125
-
50
-
15
-
125
-
50
-
15
ns
ns
ns
50
-
50
-
ns
see
Figure 20
see
Figure 20
see
Figure 20
see
Figure 20
22
22
-
-
t
CLCL
t
CLCX
t
CLCL
t
CHCX
5
5
22
22
-
-
-
-
5
5
ns
ns
ns
ns
16 t
CLCL
13 t
CLCL
-
-
888
722
-
-
ns
ns
-
t
CLCL
+ 20
-
75
ns
-
0
-
0
ns
150
-
150
-
ns
0
-
CCLK
6
CCLK
4
0
-
3
4.5
MHz
MHz
see Figures
15
,
16
,
17
,
18
3.0 MHz (Slave)
4.5 MHz (Master)
6
CCLK
4
CCLK
-
-
333
222
-
-
ns
ns
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