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參數(shù)資料
| 型號： | OR3T125-4PS208I |
| 英文描述： | 1.8V LOW COST OP AMP, -40C to +85C, 5-SOT-23, T/R |
| 中文描述： | 現(xiàn)場可編程門陣列（FPGA） |
| 文件頁數(shù)： | 16/210頁 |
| 文件大?。?/td> | 4663K |
| 代理商： | OR3T125-4PS208I |
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16
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
Half-Logic Mode
Series 3 FPGAs are based upon a twin-quad architec-
ture in the PFUs. The byte-wide nature (eight LUTs,
eight latches/FFs) may just as easily be viewed as two
nibbles (two sets of four LUTs, four latches/FFs). The
two nibbles of the PFU are organized so that any nib-
ble-wide feature (excluding some softwired LUT topolo-
gies) can be swapped with any other nibble-wide
feature in another PFU. This provides for very flexible
use of logic and for extremely flexible routing. The half-
logic mode of the PFU takes advantage of the twin-
quad architecture and allows half of a PFU, K
[7:4]
and
associated latches/FFs, to be used in logic mode while
the other half of the PFU, K
[3:0]
and associated latches/
FFs, is used in ripple mode. In half-logic mode, the
ninth FF may be used as a general-purpose FF or as a
register in the ripple mode carry chain.
Ripple Mode
The PFU LUTs can be combined to do byte-wide ripple
functions with high-speed carry logic. Each LUT has a
dedicated carry-out net to route the carry to/from any
adjacent LUT. Using the internal carry circuits, fast
arithmetic, counter, and comparison functions can be
implemented in one PFU. Similarly, each PFU has
carry-in (CIN, FCIN) and carry-out (COUT, FCOUT)
ports for fast-carry routing between adjacent PFUs.
The ripple mode is generally used in operations on two
data buses. A single PFU can support an 8-bit ripple
function. Data buses of 4 bits and less can use the
nibble-wide ripple chain that is available in half-logic
mode. This nibble-wide ripple chain is also useful for
longer ripple chains where the length modulo 8 is four
or less. For example, a 12-bit adder (12 modulo 8 = 4)
can be implemented in one PFU in ripple mode (8 bits)
and one PFU in half-logic mode (4 bits), freeing half of
a PFU for general logic mode functions.
Each LUT has two operands and a ripple (generally
carry) input, and provides a result and ripple (generally
carry) output. A single bit is rippled from the previous
LUT and is used as input into the current LUT. For LUT
K
0
, the ripple input is from the PFU CIN or FCIN port.
The CIN/FCIN data can come from either the fast-carry
routing (FCIN) or the PFU input (CIN), or it can be tied
to logic 1 or logic 0.
In the following discussions, the notations LUT K
7
/K
3
and F[7:0]/F[3:0]
are used to denote the LUT that pro-
vides the carry-out and the data outputs for full PFU
ripple operation (K
7
, F[7:0]) and half-logic ripple
operation (K
3
, F[3:0]), respectively. The ripple mode
diagram in Figure 6 shows full PFU ripple operation,
with half-logic ripple connections shown as dashed
lines.
The result output and ripple output are calculated by
using generate/propagate circuitry. In ripple mode, the
two operands are input into K
Z
[1] and K
Z
[0] of each
LUT. The result bits, one per LUT, are F[7:0]/F[3:0]
(see
Figure 6). The ripple output from LUT K
7
/K
3
can be
routed on dedicated carry circuitry into any of four adja-
cent PLCs, and it can be placed on the PFU COUT/
FCOUT outputs. This allows the PLCs to be cascaded
in the ripple mode so that nibble-wide ripple functions
can be expanded easily to any length.
Result outputs and the carry-out may optionally be reg-
istered within the PFU. The capability to register the
ripple results, including the carry output, provides for
improved counter performance and simplified pipelin-
ing in arithmetic functions.
Figure 6. Ripple Mode
5-5755(F)
F7
K
7
[1]
K
7
[0]
K
7
D
Q
C
C
D Q
Q7
REGCOUT
COUT
F6
K
6
[1]
K
6
[0]
K
6
D
Q
Q6
F4
K
4
[1]
K
4
[0]
K
4
D
Q
Q4
F3
K
3
[1]
K
3
[0]
K
3
D
Q
Q3
F2
K
2
[1]
K
2
[0]
K
2
D
Q
Q2
F1
K
1
[1]
K
1
[0]
K
1
D
Q
Q1
F5
K
5
[1]
K
5
[0]
K
5
D
Q
Q5
F0
K
0
[1]
K
0
[0]
K
0
D
Q
Q0
CIN/FCIN
FCOUT
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| OR3T125-5PS240I | Dual 1.8V, 1MHz OP, I temp, -40C to +85C, 8-PDIP, TUBE |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T125-4PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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| OR3T125-5BC432 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-5BC432I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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