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| 型號(hào)： | OR3T125-4PS208I |
| 英文描述： | 1.8V LOW COST OP AMP, -40C to +85C, 5-SOT-23, T/R |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列（FPGA） |
| 文件頁(yè)數(shù)： | 152/210頁(yè) |
| 文件大?。?/td> | 4663K |
| 代理商： | OR3T125-4PS208I |
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152
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Special-Purpose Pins
(continued)
A11/
MPI_IRQ
O
I/O
A10/
MPI_BI
O
I/O
A9/
MPI_ACK
O
MPI
active-low interrupt request output.
After configuration, if the
MPI
is not used, this pin is a user-programmable I/O pin (see Note).
PowerPC mode
MPI
burst inhibit output.
After configuration, if the
MPI
is not used, this pin is a user-programmable I/O pin (see Note).
In PowerPC mode
MPI
operation, this is the active-high transfer acknowledge (
TA
) output. For
i960
MPI
operation, it is the active-low ready/record (
RDYRCV
) output.
After configuration, if the
MPI
is not used, this pin is a user-programmable I/O pin (see Note).
In PowerPCmode
MPI
operation, this is the active-low write/active-high read control signals.
For i960operation, it is the active-high write/active-low read control signal.
After configuration, if the
MPI
is not used, this pin is a user-programmable I/O pin (see Note).
I/O
I
A8/MPI_RW
I/O
I
A7/MPI_CLK
I/O
I
This is the clock used for the synchronous
MPI
interface. For PowerPC, it is the CLKOUT
signal. For i960 it is the system clock that is chosen for the i960external bus interface.
After configuration, if the
MPI
is not used, this pin is a user-programmable I/O pin (see Note).
For PowerPC operation, these are the PowerPCaddress inputs. The address bit mapping (in
PowerPC/FPGA notation) is A[31]/A[0], A[30]/A[1], A[29]/A[2], A[28]/A[3], A[27]/A[4]. Note
that A[27]/A[4] is the MSB of the address. The A[4:2] inputs are not used in i960
MPI
mode.
After configuration, if the
MPI
is not used, this pin is a user-programmable I/O pin (see Note).
A[4:0]
I/O
I
A[1:0]/
MPI_BE[1:0]
I/O
I
For i960 operation,
MPI_BE[1:0]
provide the i960byte enable signals,
BE[1:0]
, that are used as
address bits A[1:0] in i960byte-wide operation.
After configuration, if the
MPI
is not used, this pin is a user-programmable I/O pin (see Note).
D[7:0]
I/O
I
During master parallel, peripheral, and slave parallel configuration modes, D[7:0] receive
configuration data, and each pin has a pull-up enabled. During serial configuration modes, D0
is the DIN input. D[7:0] are also the data pins for PowerPC microprocessor mode and the
address/data pins for i960microprocessor mode.
After configuration, the pins are user-programmable I/O pins (see Note).
DIN
I/O
O
During slave serial or master serial configuration modes, DIN accepts serial configuration
data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. Dur-
ing configuration, a pull-up is enabled.
After configuration, this pin is a user-programmable I/O pin (see Note).
DOUT
I/O
During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained
slave LCA devices. Data out on DOUT changes on the falling edge of CCLK.
After configuration, DOUT is a user-programmable I/O pin (see Note).
Pin Information
(continued)
Table 67. Pin Descriptions
(continued)
Symbol
I/O
Description
Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the
activation of all user I/Os) is controlled by a second set of options.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3T125-4PS240I | Field Programmable Gate Array (FPGA) |
| OR3T125-5BC432I | Field Programmable Gate Array (FPGA) |
| OR3T125-5BC600I | Dual 1.8V, 1MHz OP, -40C to +125C, 8-PDIP, TUBE |
| OR3T125-5PS208I | Dual 1.8V, 1MHz OP, I temp, -40C to +85C, 8-MSOP, TUBE |
| OR3T125-5PS240I | Dual 1.8V, 1MHz OP, I temp, -40C to +85C, 8-PDIP, TUBE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T125-4PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-5BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-5BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-5BC432 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-5BC432I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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