參數(shù)資料
型號(hào)： NSC800N
廠(chǎng)商： National Semiconductor Corporation
英文描述： NSC800TM High-Performance Low-Power CMOS Microprocessor
中文描述： NSC800TM高性能低功耗CMOS微處理器
文件頁(yè)數(shù)： 54/76頁(yè)
文件大小： 785K
代理商： NSC800N
12.12 Input/Output
(Continued)
INDR
Data is input from the I/O device at address (C) to memory
location (HL), then the HL memory pointer is byte counter B
are decremented. The cycle is repeated until B
e
0.
(Note that B is tested for zero after it is decremented. By
loading B initially with zero, 256 data transfers will take
place.)
(HL)
w
(C)
S: Undefined
HL
w
HL
b
1
Z: Set
B
w
B
b
1
H: Undefined
Repeat until B
e
0
P/V: Undefined
N: Set
C: N/A
0
7
6
5
4
3
2
1
1
1
1
0
1
1
0
1
1
0
1
1
0
0
1
0
Timing:
For B
i
0
M cycles D 5
T states D 21 (4, 5, 3, 4, 5)
For B
e
0
M cycles D 4
T states D 16 (4, 5, 3, 4)
Addressing Mode:
Implied/Source D Register In-
direct
Destination D Register Indirect
(Note that after each data transfer cycle, interrupts may be
recognized and two refresh cycles are performed.)
OTDR
Data is output from memory location (HL) to the I/O device
at port address (C), then the HL memory pointer and byte
counter B are decremented. The cycle is repeated until B
e
0.
(Note that B is tested for zero after it is decremented. By
loading B initially with zero, 256 data transfers will take
place.)
(C)
w
(HL)
S: Undefined
HL
w
HL
b
1
Z: Set
B
w
B
b
1
H: Undefined
Repeat until B
e
0
P/V: Undefined
N: Set
C: N/A
0
7
6
5
4
3
2
1
1
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
Timing:
For B
i
0
M cycles D 5
T states D 21 (4, 5, 3, 4, 5)
For B
e
0
M cycles D 4
T states D 16 (4, 5, 3, 4)
Addressing Mode:
Implied/Source D Register In-
direct
Destination D Register Indirect
(Note that after each data transfer cycle the NSC800 will
accept interrupts and perform two refresh cycles.)
12.13 CPU Control
NOP
The CPU performs no operation.
D D D
7
No flags affected
0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Timing:
M cycles D 1
T states D 4
Addressing Mode:
N/A
HALT
The CPU halts execution of the program. Dummy op-code
fetches are performed from the next memory location to
keep the refresh circuits active until the CPU is interrupted
or reset from the halted state.
D D D
7
No flags affected
0
6
5
4
3
2
1
0
1
1
1
0
1
1
0
Timing:
M cycles D 1
T states D 4
Addressing Mode:
N/A
DI
Disable system level interrupts.
IFF
1
w
0
IFF
2
w
0
7
6
5
4
No flags affected
3
2
1
0
1
1
1
1
0
0
1
1
Timing:
M cycles D 1
T states D 4
Addressing Mode:
N/A
EI
The system level interrupts are enabled. During execution of
this instruction, and the next one, the maskable interrupts
will be disabled.
IFF
1
w
1
No flags affected
IFF
2
w
1
7
6
5
4
3
2
1
0
1
1
1
1
1
0
1
1
Timing:
M cycles D 1
T states D 4
Addressing Mode:
N/A
IM
0
The CPU is placed in interrupt mode 0.
D D D
7
No flags affected
0
6
5
4
3
2
1
1
1
1
0
1
1
0
1
0
1
0
0
0
1
1
0
Timing:
M cycles D 2
T states D 8 (4, 4)
Addressing Mode:
N/A
54
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NSC800N/A+ 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:8-Bit Microprocessor
NSC800N/B+ 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:8-Bit Microprocessor
NSC800N-1 制造商:Texas Instruments 功能描述:
NSC800N-1/A+ 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:8-Bit Microprocessor
NSC800N-1/B+ 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:8-Bit Microprocessor
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