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參數(shù)資料
| 型號： | NSC800N |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | NSC800TM High-Performance Low-Power CMOS Microprocessor |
| 中文描述： | NSC800TM高性能低功耗CMOS微處理器 |
| 文件頁數(shù)： | 41/76頁 |
| 文件大小： | 785K |
| 代理商： | NSC800N |
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12.6 8-Bit Arithmetic
(Continued)
7
6
5
4
3
2
1
0
1
0
0
1
0
1
1
0
SUB (HL)
Timing:
M cyclesD2
T statesD7 (4, 3)
Addressing Mode:
SourceDRegister Indirect
DestinationDImplied
0
SUB (IX
a
d) (for N
X
e
0)
1
SUB (IY
a
d) (for N
X
e
1)
7
6
5
4
3
2
1
1
1
N
X
1
1
1
0
1
0
0
1
0
1
1
0
d
Timing:
M cyclesD5
T statesD19 (4, 4, 3, 5, 3)
Addressing Mode:
SourceDIndexed
DestinationDImplied
SBC
A, m
1
Subtract, with carry, the contents of memory location m
1
from the Accumulator.
A
w
A
b
m
1
b
CY
S: Set if result is negative
Z: Set if result is zero
H: Set if carry from bit 3
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Set
C: Set according to borrow
condition
0
7
6
5
4
3
2
1
1
0
0
1
1
1
1
0
SBC A, (HL)
Timing:
M cyclesD2
T statesD7 (4, 3)
Addressing Mode:
SourceDRegister Indirect
DestinationDImplied
7
6
5
4
3
2
1
0
SBC A, (IX
a
d) (for N
X
e
0)
1
1
N
X
1
1
1
0
1
SBC A, (IY
a
d) (for N
X
e
1)
1
0
0
1
1
1
1
0
d
Timing:
M cyclesD5
T statesD19 (4, 4, 3, 5, 3)
Addressing Mode:
SourceDIndexed
DestinationDImplied
AND
m
1
The data in memory location m
1
is logically AND’ed to the
Accumulator.
A
w
A
!
m
1
S: Set if result is negative
Z: Set if result is zero
H: Set
P/V: Set if result parity is even
N: Reset
C: Reset
0
7
6
5
4
3
2
1
1
0
1
0
0
1
1
0
AND (HL)
Timing:
M cyclesD2
T statesD7 (4, 3)
Addressing Mode:
SourceDRegister Indirect
DestinationDImplied
0
AND (IX
a
d) (for N
X
e
0)
1
AND (IY
a
d) (for N
X
e
1)
7
6
5
4
3
2
1
1
1
N
X
1
1
1
0
1
0
1
0
0
1
1
0
d
Timing:
M cyclesD5
T statesD19 (4, 4, 3, 5, 3)
Addressing Mode:
SourceDIndexed
DestinationDImplied
OR
m
1
The data in memory location m
1
is logically OR’ed with the
Accumulator.
A
w
A
m
1
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Reset
0
7
6
5
4
3
2
1
1
0
1
1
0
1
1
0
OR (HL)
Timing:
M cyclesD2
T statesD7 (4, 3)
Addressing Mode:
SourceDRegister Indexed
DestinationDImplied
0
OR (IX
a
d) (for N
X
e
0)
1
OR (IY
a
d) (for N
X
e
1)
7
6
5
4
3
2
1
1
1
N
X
1
1
1
0
1
0
1
1
0
1
1
0
d
Timing:
M cyclesD5
T statesD19 (4, 4, 3, 5, 3)
Addressing Mode:
SourceDIndexed
DestinationDImplied
41
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| NSC800V | NSC800TM High-Performance Low-Power CMOS Microprocessor |
| NSC858 | NSC858 Universal Asynchronous Receiver/Transmitter |
| NSC858D | NSC858 Universal Asynchronous Receiver/Transmitter |
| NSC858E | NSC858 Universal Asynchronous Receiver/Transmitter |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| NSC800N/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microprocessor |
| NSC800N/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microprocessor |
| NSC800N-1 | 制造商:Texas Instruments 功能描述: |
| NSC800N-1/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microprocessor |
| NSC800N-1/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microprocessor |
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