
12.6 8-Bit Arithmetic
(Continued)
7
6
5
4
3
2
1
0
0
0
1
1
0
1
0
1
DEC (HL)
Timing:
M cycles D 3
T states D 11 (4, 4, 3)
Addressing Mode:
Source D Register Indexed
Destination
dexed
D
Register
In-
7
6
5
4
3
2
1
0
DEC (IX
a
d) (for N
X
e
0)
1
1
N
X
1
1
1
0
1
DEC (IY
a
d) (for N
X
e
1)
0
0
1
1
0
1
0
1
d
Timing:
M cycles D 6
T states D 23 (4, 4, 3, 5, 4, 3)
Addressing Mode:
Source D Indexed
Destination D Indexed
12.7 16-Bit Arithmetic
ADD
ss, pp
Add the contents of the 16-bit register rp or pp to the con-
tents of the 16-bit register ss.
ss
w
ss
a
rp
S: N/A
or
Z: N/A
ss
w
ss
a
pp
H: Set if carry from bit 11
P/V: N/A
N: Reset
C: Set if carry from bit 15
2
1
0
7
6
5
4
3
0
0
rp
1
0
0
1
ADD HL, rp
Timing:
M cycles D 3
T states D 11 (4, 4, 3)
Addressing Mode:
Source D Register
Destination D Register
1
0
ADD IX, pp (for N
X
e
0)
0
1
ADD IY, pp (for N
X
e
1)
7
6
5
4
3
2
1
1
N
X
1
1
1
0
0
pp
1
0
0
1
Timing:
M cycles D 4
T states D 15 (4, 4, 4, 3)
Addressing Mode:
Source D Register
Destination D Register
ADC
HL, pp
The contents of the 16-bit register pp are added, with the
carry bit, to the HL register.
HL
w
HL
a
pp
a
CY
S: Set if result is negative
Z: Set if result is zero
H: Set according to carry out of bit
11
P/V: Set if result exceeds 16-bit 2’s
complement range
N: Reset
C: Set if carry out of bit 15
1
0
7
6
5
4
3
2
1
1
1
0
1
1
0
1
0
1
pp
1
0
1
0
Timing:
M cycles D 4
T states D 15 (4, 4, 4, 3)
Addressing Mode:
Source D Register
Destination D Register
SBC
HL, pp
Subtract, with carry, the contents of the 16-bit pp register
from the 16-bit HL register.
HL
w
HL
b
pp
b
CY
S: Set if result is negative
Z: Set if result is zero
H: Set according to borrow from
bit 12
P/V: Set if result exceeds 16-bit 2’s
complement range
N: Set
C: Set according to borrow condi-
tion
1
0
7
6
5
4
3
2
1
1
1
0
1
1
0
1
0
1
pp
0
0
1
0
Timing:
M cycles D 4
T states D 15 (4, 4, 4, 3)
Addressing Mode:
Source D Register
Destination D Register
INC
rr
Increment the contents of the 16-bit register rr.
rr
w
rr
a
1
7
6
5
4
3
2
No flags affected
0
INC BC
INC DE
INC HL
INC SP
1
0
0
rp
0
0
1
1
Timing:
M cycles D 1
T states D 6
Addressing Mode:
7
6
Register
0
5
4
3
2
1
INC IX (for N
X
e
0)
1
1
N
X
1
1
1
0
1
INC IY (for N
X
e
1)
0
0
1
0
0
0
1
1
Timing:
M cycles D 2
T states D 10 (4, 6)
Addressing Mode:
Register
43