
12.6 8-Bit Arithmetic
(Continued)
XOR
m
1
The data in memory location m
1
is exclusively OR’ed with
the data in the Accumulator.
A
w
A
Z
m
1
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Reset
0
7
6
5
4
3
2
1
1
0
1
0
1
1
1
0
XOR (HL)
Timing:
M cyclesD2
T statesD7 (4, 3)
Addressing Mode:
SourceDRegister Indexed
DestinationDImplied
0
XOR (IX
a
d) (for N
X
e
0)
1
XOR (IY
a
d) (for N
X
e
1)
7
6
5
4
3
2
1
1
1
N
X
1
1
1
0
1
0
1
0
1
1
1
0
d
Timing:
M cyclesD5
T statesD19 (4, 4, 3, 5, 3)
Addressing Mode:
SourceDIndexed
DestinationDImplied
CP
m
1
Compare the data in memory location m
1
with the data in
the Accumulator via subtraction.
A
b
m
1
S: Set if result is negative
Z: Set if result is zero
H: Set if borrow from bit 4
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Set
C: Set according to borrow
condition
0
7
6
5
4
3
2
1
1
0
1
1
1
1
1
0
CP (HL)
Timing:
M cyclesD2
T statesD7 (4, 3)
Addressing Mode:
SourceDRegister Indirect
DestinationDImplied
0
CP (IX
a
d) (for N
X
e
0)
1
CP (IY
a
d) (for N
X
e
1)
7
6
5
4
3
2
1
1
1
N
X
1
1
1
0
1
0
1
1
1
1
1
0
d
Timing:
M cyclesD5
T statesD19 (4, 4, 3, 5, 3)
Addressing Mode:
SourceDIndexed
DestinationDImplied
INC
m
1
Increment data in memory location m
1
.
m
1
w
m
1
a
1
S: Set if result is negative
Z: Set if result is zero
H: Set according to carry from bit
3
P/V: Set if data was X’7F before op-
eration
N: Reset
C: N/A
0
7
6
5
4
3
2
1
0
0
1
1
0
1
0
0
INC (HL)
Timing:
M cyclesD3
T statesD11 (4, 4, 3)
Addressing Mode:
SourceDRegister Indexed
DestinationDRegister Indexed
0
INC (IX
a
d) (for N
X
e
0)
1
INC (IY
a
d) (for N
X
e
1)
7
6
5
4
3
2
1
1
1
N
X
1
1
1
0
0
0
1
1
0
1
0
0
d
Timing:
M cyclesD6
T statesD23 (4, 4, 3, 5, 4, 3)
Addressing Mode:
SourceDIndexed
DestinationDIndexed
DEC
m
1
Decrement data in memory location m
1
.
m
1
w
m
1
b
1
S: Set if result is negative
Z: Set if result is zero
H: Set according to borrow from
bit 4
P/V: Set only if m
1
was X’80 before
operation
N: Set
C: N/A
42