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| 型號： | NSAM265SRA |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | CompactSPEECH Digital Speech Processors |
| 中文描述： | CompactSPEECH數(shù)字語音處理器 |
| 文件頁數(shù)： | 40/58頁 |
| 文件大?。?/td> | 712K |
| 代理商： | NSAM265SRA |
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Appendix A Device Specifications
(Continued)
TABLE A-2. Timing for Output Signals
(Continued)
Symbol
Figure
Description
Reference Conditions
Min (ns)
Max (ns)
t
RASh
A-10
RAS Hold
After R.E. CTTL
0.0
t
RASia
A-10
RAS Inactive
After R.E. CTTL, T3 or T3RF
12.0
t
RASLw
A-13
DRAM PDM, RAS Width
At 0.8V, Both Edges
200.0
t
RLCL
A-13
DRAM PDM RAS Low, after CAS Low
F.E. CAS to F.E. RAS
200.0
t
WRa
A-17
WR0 Active
After R.E. CTTL, T1
t
CTp
/2
a
12
t
WRCSh
A-17
WR0 Hold after EMCS (Note B)
R.E. EMCS R.E. to R.E. WR0
10.0
t
WRh
A-17
WR0 Hold
After R.E. CTTL
t
CTp
/2
b
6
t
WRia
A-17
WR0 Inactive
After R.E. CTTL, T3
t
CTp
/2
a
12
Note A:
In normal operation t
CTp
must be 48.8 ns; in power-down mode, t
CTp
must be 50,000 ns.
Note B:
Guaranteed by design, but not fully tested.
Table A-3. Input Signals
Symbol
Figure
Description
Reference Conditions
Min (ns)
t
CDIh
A-14
CDIN Hold
After R.E. CTTL
0.0
t
CDIs
A-14
CDIN Setup
Before R.E. CTTL
11.0
t
DIh
A-10
Data in Hold (D0:7)
After R.E. CTTL T1, T3 or TI
0.0
t
DIs
A-10
Data in Setup (D0:7)
Before R.E. CTTL T1, T3 or TI
15.0
t
MWCKh
A-18
MICROWIRE Clock High (Slave)
At 2.0V (Both Edges)
100.0
t
MWCKI
A-18
MICROWIRE Clock Low (Slave)
At 0.8V (Both Edges)
100.0
t
MWCKp
A-18
MICROWIRE Clock Period (Slave) (Note A)
R.E. MWCLK to next R.E. MWCLK
2.5 ms
t
MWCLKh
A-18
MWCLK Hold
After MWCS becomes Inactive
50.0
t
MWCLKs
A-18
MWCLK Setup
Before MWCS becomes Active
100
t
MWCSh
A-18
MWCS Hold
After F.E. MWCLK
50.0
t
MWCSs
A-18
MWCS Setup
Before R.E. MWCLK
100.0
t
MWDIh
A-18
MWDIN Hold
After R.E. MWCLK
50.0
t
MWDIs
A-18
MWDIN Setup
Before R.E. MWCLK
100.0
t
PWR
A-23
Power Stable to RESET R.E. (Note B)
After V
CC
reaches 4.5V
30 ms
t
RSTw
A-22
RESET Pulse Width
At 0.8V (Both Edges)
10 ms
t
Xh
A-21
CLKIN High
At 2.0V (Both Edges)
t
X1p
/2
b
5
t
XI
A-21
CLKIN Low
At 0.8V (Both Edges)
t
X1p
/2
b
5
t
Xp
A-21
CLKIN Clock Period
R.E. CLKIN to next R.E. CLKIN
24.4
Note A:
Guaranteed by design, but not fully tested in power-down mode.
Note B:
Guaranteed by design. but not fully tested.
40
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