參數(shù)資料
型號(hào)： NSAM265SRA
廠商： National Semiconductor Corporation
英文描述： CompactSPEECH Digital Speech Processors
中文描述： CompactSPEECH數(shù)字語(yǔ)音處理器
文件頁(yè)數(shù)： 32/58頁(yè)
文件大?。?/td> 712K
代理商： NSAM265SRA
Appendix A
Device Specifications
This appendix describes the pins and signals of the
NSAM265SR and NSAM265SF CompactSPEECH proces-
sors, specifies its maximum ratings and its electrical charac-
teristics, and describes its timing.
A.1 PIN ASSIGNMENT
The following sections list the pins of the NSAM265SR and
NSAM265SF CompactSPEECH processors. They indicate
which signals use the same pin and under what conditions
each signal is enabled for that pin. Slashes separate the
names of signals that share the same pin.
A.1.1 Pin-Signal Assignment
Table A-1 shows all the pins, and the signals that use them
in different configurations. It also shows the type and direc-
tion of each signal.
TABLE A-1. CompactSPEECH Pin-Signal Assignment under Different Conditions
Pin Name
Type
Signal Name
I/O
A(0:15)
TTL
A(0:15)
Output
CAS (Note A)
TTL1 (Note B)
CAS
Output
CCLK
TTL
CCLK
Output
CDIN
TTL
CDIN
Input
CDOUT
TTL
CDOUT
Output
CFS0
TTL
CFS0
Output
D(0:1)
TTL
D(0:1)
I/O
D2/RA11
TTL
D2/RA11
I/O
D(3:7)
TTL
D(3:7)
I/O
DWE
TTL1 (Note B)
DWE
Output
MWCS
TTL (Note C)
MWCS
Input
WR0/TST
TTL
WR0
TST
Output
Input
MWDRY
TTL
MWDRY
I/O
MWRQST
TTL
MWRQST
I/O
MWDOUT
TTL
MWDOUT
Output
PB(0:5) (Note D)
TTL
EA(16:21)
Output
PB6 (Note E)
TTL
AFLASHDOE
Output
EMCS/ENV0
TTL1 (Note B)
EMCS
Output
CMOS (Note F)
ENV0
Input
MWCLK
TTL
MWCLK
Input
MWDIN
TTL
MWDIN
Input
RAS (Note A)
TTL1 (Note B)
RAS
Output
RESET
Schmitt (Note C)
RESET
Input
V
CC
Power
V
CC
V
SS
Power
V
SS
X1
XTAL
X1
OSC
X2/CLKIN
XTAL
TTL
X2
CLKIN
OSC
Input
Note A:
Used in NSAM265SR only. N.C. in NSAM265SF.
Note B:
TTL1 output signals provide CMOS levels in the steady state, for small loads.
Note C:
Schmitt trigger input.
Note D:
NSAM265SR and NSAM265SFDvirtual address lines for IVS ROM.
NSAM265SF onlyDvirtual address lines for FLASH.
Note E:
Used in NSAM265SF onlyDenables/disable FLASH.
Note F:
Input during reset, CMOS level input.
32
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